50use ieee.std_logic_1164.
all;
51use ieee.numeric_std.
all;
101 signal CP_CNTL : cp_cntl_type := cp_cntl_init;
102 signal CP_ADDR : cp_addr_type := cp_addr_init;
109 signal EM_MREQ : em_mreq_type := em_mreq_init;
110 signal EM_SRES : em_sres_type := em_sres_init;
191 TWIDTH => sys_conf_cache_twidth
)
214 HM_VAL => DM_STAT_CA.rdhit,
223 IBMON : if sys_conf_ibmon_awidth > 0 generate
228 AWIDTH => sys_conf_ibmon_awidth
)
238 IBTST : if sys_conf_ibtst generate
262 DMSCNT : if sys_conf_dmscnt generate
278 DMCMON : if sys_conf_dmcmon_awidth > 0 generate
283 AWIDTH => sys_conf_dmcmon_awidth,
284 SNUM => sys_conf_dmscnt
)
297 DMHBPT : if sys_conf_dmhbpt_nunit > 0 generate
302 NUNIT => sys_conf_dmhbpt_nunit
)
316 DMPCNT : if sys_conf_dmpcnt generate
322 variable isig : slv32 := (others=>'0');
325 isig := (others=>'0');
391 end process proc_sig;
397 VERS =>
slv(to_unsigned
(1,
8)),
400 CENA => "
11111111111111111111111111111111"
)
in IB_SRES_2 ib_sres_type := ib_sres_init
in IB_SRES_3 ib_sres_type := ib_sres_init
out IB_SRES_OR ib_sres_type
in IB_SRES_4 ib_sres_type := ib_sres_init
in IB_SRES_1 ib_sres_type
in IB_SRES_SUM ib_sres_type
IB_ADDR slv16 := slv( to_unsigned( 8#160000#, 16) )
IB_ADDR slv16 := slv( to_unsigned( 8#170000#, 16) )
out DM_STAT_CA dm_stat_ca_type
RB_ADDR_CORE slv16 := rbaddr_cpu0_core
RB_ADDR_IBUS slv16 := rbaddr_cpu0_ibus
in IB_SRES_M ib_sres_type
out DM_STAT_DP dm_stat_dp_type
out DM_STAT_CO dm_stat_co_type
out IB_MREQ_M ib_mreq_type
out DM_STAT_VM dm_stat_vm_type
out DM_STAT_SE dm_stat_se_type
in DM_STAT_DP dm_stat_dp_type
in DM_STAT_CO dm_stat_co_type
RB_ADDR slv16 := rbaddr_dmcmon_off
in DM_STAT_SE dm_stat_se_type
in DM_STAT_VM dm_stat_vm_type
in DM_STAT_DP dm_stat_dp_type
in DM_STAT_CO dm_stat_co_type
in DM_STAT_SE dm_stat_se_type
RB_ADDR slv16 := rbaddr_dmhbpt_off
in DM_STAT_VM dm_stat_vm_type
CENA slv32 :=( others => '1')
VERS slv8 := slv( to_unsigned( 1, 8) )
RB_ADDR slv16 := rbaddr_dmpcnt_off
in DM_STAT_DP dm_stat_dp_type
in DM_STAT_CO dm_stat_co_type
in DM_STAT_SE dm_stat_se_type
RB_ADDR slv16 := rbaddr_dmscnt_off
rb_sres_type := rb_sres_init RB_SRES_DMCMON
dm_stat_se_type := dm_stat_se_init DM_STAT_SE
slv32 :=( others => '0') PERFSIG
rb_sres_type := rb_sres_init RB_SRES_DMPCNT
dm_stat_dp_type := dm_stat_dp_init DM_STAT_DP
dm_stat_vm_type := dm_stat_vm_init DM_STAT_VM
slv16 := x"4000" rbaddr_ibus0
rb_sres_type := rb_sres_init RB_SRES_DMHBPT
slv16 :=( others => '0') CP_DOUT
slv16 := x"0000" rbaddr_core0
em_sres_type := em_sres_init EM_SRES
slv16 :=( others => '0') CP_DIN
cp_stat_type := cp_stat_init CP_STAT_L
dm_stat_co_type := dm_stat_co_init DM_STAT_CO
ib_sres_type := ib_sres_init IB_SRES_IBTST
rb_sres_type := rb_sres_init RB_SRES_DMSCNT
rb_sres_type := rb_sres_init RB_SRES_L
rb_sres_type := rb_sres_init RB_SRES_CORE
ib_mreq_type := ib_mreq_init IB_MREQ_M
ib_sres_type := ib_sres_init IB_SRES_IBMON
cp_addr_type := cp_addr_init CP_ADDR
ib_sres_type := ib_sres_init IB_SRES_M
cp_cntl_type := cp_cntl_init CP_CNTL
em_mreq_type := em_mreq_init EM_MREQ
rb_sres_type := rb_sres_init RB_SRES_DM
dm_stat_ca_type := dm_stat_ca_init DM_STAT_CA
ib_sres_type := ib_sres_init IB_SRES_MEM70
out DM_STAT_EXP dm_stat_exp_type
in DM_STAT_DP dm_stat_dp_type
in DM_STAT_CO dm_stat_co_type
in DM_STAT_SE dm_stat_se_type
in DM_STAT_VM dm_stat_vm_type
in DM_STAT_CA dm_stat_ca_type
ENAPIN integer := sbcntl_sbf_tmu
in RB_SRES_2 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
in RB_SRES_2 rb_sres_type := rb_sres_init
in RB_SRES_3 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
in RB_SRES_4 rb_sres_type := rb_sres_init
std_logic_vector( 19 downto 0) slv20
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 8 downto 2) slv9_2
std_logic_vector( 31 downto 0) slv32
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8