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W11 CPU core and support modules
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sys_tst_mig_arty.vhd
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1-- $Id: sys_tst_mig_arty.vhd 1247 2022-07-06 07:04:33Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2018-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_tst_mig_arty - syn
7-- Description: test of arty ddr and its mig controller
8--
9-- Dependencies: vlib/xlib/bufg_unisim
10-- bplib/bpgen/s7_cmt_1ce1ce2c
11-- cdclib/cdc_signal_s1_as
12-- cdclib/cdc_pulse
13-- bplib/bpgen/bp_rs232_2line_iob
14-- rlink/rlink_sp2c
15-- tst_mig
16-- bplib/arty/migui_arty (generated core)
17-- bplib/sysmon/sysmonx_rbus_arty
18-- rbus/rbd_usracc
19-- rbus/rb_sres_or_3
20--
21-- Test bench: tb/tb_tst_mig_arty
22--
23-- Target Devices: generic
24-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0
25--
26-- Synthesized (viv):
27-- Date Rev viv Target flop lutl lutm bram slic
28-- 2022-07-05 1247 2022.1 xc7a35t-1l 4325 4197 415 1 1699
29-- 2019-02-02 1108 2018.3 xc7a35t-1l 4323 4537 444 1 1874
30-- 2019-02-02 1108 2017.2 xc7a35t-1l 4330 4773 444 1 1774
31-- 2019-01-02 1101 2017.2 xc7a35t-1l 4320 4773 462 1 1770
32--
33-- Revision History:
34-- Date Rev Version Comment
35-- 2022-07-05 1247 1.0.1 use bufg_unisim
36-- 2018-12-26 1094 1.0 Initial version
37-- 2018-12-23 1092 0.1 First draft
38------------------------------------------------------------------------------
39
40library ieee;
41use ieee.std_logic_1164.all;
42use ieee.numeric_std.all;
43
44use work.slvtypes.all;
45use work.xlib.all;
46use work.cdclib.all;
47use work.serportlib.all;
48use work.rblib.all;
49use work.rbdlib.all;
50use work.rlinklib.all;
51use work.bpgenlib.all;
52use work.sysmonrbuslib.all;
53use work.miglib_arty.all;
54use work.sys_conf.all;
55
56-- ----------------------------------------------------------------------------
57
58entity sys_tst_mig_arty is -- top level
59 -- implements arty_mig_aif
60 port (
61 I_CLK100 : in slbit; -- 100 MHz clock
62 I_RXD : in slbit; -- receive data (board view)
63 O_TXD : out slbit; -- transmit data (board view)
64 I_SWI : in slv4; -- arty switches
65 I_BTN : in slv4; -- arty buttons
66 O_LED : out slv4; -- arty leds
67 O_RGBLED0 : out slv3; -- arty rgb-led 0
68 O_RGBLED1 : out slv3; -- arty rgb-led 1
69 O_RGBLED2 : out slv3; -- arty rgb-led 2
70 O_RGBLED3 : out slv3; -- arty rgb-led 3
71 A_VPWRN : in slv4; -- arty pwrmon (neg)
72 A_VPWRP : in slv4; -- arty pwrmon (pos)
73 DDR3_DQ : inout slv16; -- dram: data in/out
74 DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
75 DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
76 DDR3_ADDR : out slv14; -- dram: address
77 DDR3_BA : out slv3; -- dram: bank address
78 DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
79 DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
80 DDR3_WE_N : out slbit; -- dram: write enable (act.low)
81 DDR3_RESET_N : out slbit; -- dram: reset (act.low)
82 DDR3_CK_P : out slv1; -- dram: clock (diff-p)
83 DDR3_CK_N : out slv1; -- dram: clock (diff-n)
84 DDR3_CKE : out slv1; -- dram: clock enable
85 DDR3_CS_N : out slv1; -- dram: chip select (act.low)
86 DDR3_DM : out slv2; -- dram: data input mask
87 DDR3_ODT : out slv1 -- dram: on-die termination
88 );
90
91architecture syn of sys_tst_mig_arty is
92
93 signal CLK100_BUF : slbit := '0';
94
95 signal XX_CLK : slbit := '0'; -- kept to keep clock setup similar
96 signal XX_CE_USEC : slbit := '0'; -- to w11a or other 'normal' systems
97 signal XX_CE_MSEC : slbit := '0'; --
98
99 signal CLK : slbit := '0';
100 signal CE_USEC : slbit := '0';
101 signal CE_MSEC : slbit := '0';
102
103 signal CLKS : slbit := '0';
104 signal CES_MSEC : slbit := '0';
105
106 signal CLKMIG : slbit := '0';
107 signal CLKREF : slbit := '0';
108
109 signal LOCKED : slbit := '0'; -- raw LOCKED
110 signal LOCKED_CLKMIG : slbit := '0'; -- sync'ed to CLKMIG
111
112 signal MEM_RESET : slbit := '0';
113 signal MEM_RESET_RRI : slbit := '0';
114
115 signal RXD : slbit := '1';
116 signal TXD : slbit := '0';
117
118 signal SWI : slv16 := (others=>'0');
119 signal BTN : slv5 := (others=>'0');
120 signal LED : slv16 := (others=>'0');
121 signal DSP_DAT : slv32 := (others=>'0');
122 signal DSP_DP : slv8 := (others=>'0');
123
124 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
125 signal RB_SRES : rb_sres_type := rb_sres_init;
126 signal RB_LAM : slv16 := (others=>'0');
127 signal RB_STAT : slv4 := (others=>'0');
128
129 signal SER_MONI : serport_moni_type := serport_moni_init;
130
131 signal RB_SRES_TST : rb_sres_type := rb_sres_init;
132 signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
133 signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
134
135 signal RB_LAM_TST : slbit := '0';
136
137 signal APP_ADDR : slv(mig_mawidth-1 downto 0) := (others=>'0');
138 signal APP_CMD : slv3 := (others=>'0');
139 signal APP_EN : slbit := '0';
140 signal APP_WDF_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
141 signal APP_WDF_END : slbit := '0';
142 signal APP_WDF_MASK : slv(mig_mwidth-1 downto 0) := (others=>'0');
143 signal APP_WDF_WREN : slbit := '0';
144 signal APP_RD_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
145 signal APP_RD_DATA_END : slbit := '0';
146 signal APP_RD_DATA_VALID : slbit := '0';
147 signal APP_RDY : slbit := '0';
148 signal APP_WDF_RDY : slbit := '0';
149 signal APP_SR_REQ : slbit := '0';
150 signal APP_REF_REQ : slbit := '0';
151 signal APP_ZQ_REQ : slbit := '0';
152 signal APP_SR_ACTIVE : slbit := '0';
153 signal APP_REF_ACK : slbit := '0';
154 signal APP_ZQ_ACK : slbit := '0';
155 signal MIG_UI_CLK : slbit := '0';
156 signal MIG_UI_CLK_SYNC_RST : slbit := '0';
158 signal MIG_SYS_RST : slbit := '0';
159
160 signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
161
162 signal R_DIMCNT : slv2 := (others=>'0');
163 signal R_DIMFLG : slbit := '0';
164
165 constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
166 constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
167
168 constant sysid_proj : slv16 := x"0105"; -- tst_mig
169 constant sysid_board : slv8 := x"07"; -- arty
170 constant sysid_vers : slv8 := x"00";
171
172begin
173
174 CLK100_BUFG: bufg_unisim
175 port map (
176 I => I_CLK100,
177 O => CLK100_BUF
178 );
179
180 GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
181 generic map (
182 CLKIN_PERIOD => 10.0,
183 CLKIN_JITTER => 0.01,
184 STARTUP_WAIT => false,
185 CLK0_VCODIV => sys_conf_clksys_vcodivide,
186 CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
187 CLK0_OUTDIV => sys_conf_clksys_outdivide,
188 CLK0_GENTYPE => sys_conf_clksys_gentype,
189 CLK0_CDUWIDTH => 7,
190 CLK0_USECDIV => sys_conf_clksys_mhz,
191 CLK0_MSECDIV => 1000,
192 CLK1_VCODIV => sys_conf_clkser_vcodivide,
193 CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
194 CLK1_OUTDIV => sys_conf_clkser_outdivide,
195 CLK1_GENTYPE => sys_conf_clkser_gentype,
196 CLK1_CDUWIDTH => 7,
197 CLK1_USECDIV => sys_conf_clkser_mhz,
198 CLK1_MSECDIV => 1000,
199 CLK23_VCODIV => 1,
200 CLK23_VCOMUL => 10, -- vco 1000 MHz
201 CLK2_OUTDIV => 6, -- mig sys 166.6 MHz
202 CLK3_OUTDIV => 5, -- mig ref 200.0 MHz
203 CLK23_GENTYPE => "PLL")
204 port map (
205 CLKIN => CLK100_BUF,
206 CLK0 => XX_CLK,
207 CE0_USEC => XX_CE_USEC,
208 CE0_MSEC => XX_CE_MSEC,
209 CLK1 => CLKS,
210 CE1_USEC => open,
211 CE1_MSEC => CES_MSEC,
212 CLK2 => CLKMIG,
213 CLK3 => CLKREF,
214 LOCKED => LOCKED
215 );
216
217 -- Note: CLK0 is generated as in 'normal' systems to keep PPL/MMCM setup
218 -- as similar as possible. The CE_USEC and CE_MSEC pulses are forwarded
219 -- from the 80 MHz CLK0 domain to the 83.333 MHz MIG UI_CLK domain
220
221 CDC_CEUSEC : cdc_pulse -- provide CLK side CE_USEC
222 generic map (
223 POUT_SINGLE => true,
224 BUSY_WACK => false)
225 port map (
226 CLKM => XX_CLK,
227 RESET => '0',
228 CLKS => CLK,
229 PIN => XX_CE_USEC,
230 BUSY => open,
231 POUT => CE_USEC
232 );
233
234 CDC_CEMSEC : cdc_pulse -- provide CLK side CE_MSEC
235 generic map (
236 POUT_SINGLE => true,
237 BUSY_WACK => false)
238 port map (
239 CLKM => XX_CLK,
240 RESET => '0',
241 CLKS => CLK,
242 PIN => XX_CE_MSEC,
243 BUSY => open,
244 POUT => CE_MSEC
245 );
246
247 CDC_CLKMIG_LOCKED : cdc_signal_s1_as
248 port map (
249 CLKO => CLKMIG,
250 DI => LOCKED,
252 );
253
254 IOB_RS232 : bp_rs232_2line_iob
255 port map (
256 CLK => CLKS,
257 RXD => RXD,
258 TXD => TXD,
259 I_RXD => I_RXD,
260 O_TXD => O_TXD
261 );
262
263 RLINK : rlink_sp2c
264 generic map (
265 BTOWIDTH => 8, -- 256 cycles, for slow mem iface
266 RTAWIDTH => 12,
267 SYSID => sysid_proj & sysid_board & sysid_vers ,
268 IFAWIDTH => 5, -- 32 word input fifo
269 OFAWIDTH => 5, -- 32 word output fifo
270 ENAPIN_RLMON => sbcntl_sbf_rlmon,
271 ENAPIN_RBMON => sbcntl_sbf_rbmon,
272 CDWIDTH => 12,
273 CDINIT => sys_conf_ser2rri_cdinit,
274 RBMON_AWIDTH => 0,
276 port map (
277 CLK => CLK,
278 CE_USEC => CE_USEC,
279 CE_MSEC => CE_MSEC,
280 CE_INT => CE_MSEC,
281 RESET => '0', -- FIXME: no RESET
282 CLKS => CLKS,
284 ENAXON => '1',
285 ESCFILL => '0',
286 RXSD => RXD,
287 TXSD => TXD,
288 CTS_N => '0',
289 RTS_N => open,
290 RB_MREQ => RB_MREQ,
291 RB_SRES => RB_SRES,
292 RB_LAM => RB_LAM,
293 RB_STAT => RB_STAT,
294 RL_MONI => open,
296 );
297
298 TST : entity work.tst_mig
299 generic map (
300 RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
301 MAWIDTH => mig_mawidth,
302 MWIDTH => mig_mwidth)
303 port map (
304 CLK => CLK,
305 CE_USEC => CE_USEC,
306 RESET => '0', -- FIXME: no RESET
307 RB_MREQ => RB_MREQ,
309 RB_STAT => RB_STAT,
312 APP_CMD => APP_CMD,
313 APP_EN => APP_EN,
321 APP_RDY => APP_RDY,
332 );
333
334 MIG_CTL: migui_arty -- MIG iface -----------------
335 port map (
336 DDR3_DQ => DDR3_DQ,
337 DDR3_DQS_P => DDR3_DQS_P,
338 DDR3_DQS_N => DDR3_DQS_N,
339 DDR3_ADDR => DDR3_ADDR,
340 DDR3_BA => DDR3_BA,
341 DDR3_RAS_N => DDR3_RAS_N,
342 DDR3_CAS_N => DDR3_CAS_N,
343 DDR3_WE_N => DDR3_WE_N,
344 DDR3_RESET_N => DDR3_RESET_N,
345 DDR3_CK_P => DDR3_CK_P,
346 DDR3_CK_N => DDR3_CK_N,
347 DDR3_CKE => DDR3_CKE,
348 DDR3_CS_N => DDR3_CS_N,
349 DDR3_DM => DDR3_DM,
350 DDR3_ODT => DDR3_ODT,
351 APP_ADDR => APP_ADDR,
352 APP_CMD => APP_CMD,
353 APP_EN => APP_EN,
354 APP_WDF_DATA => APP_WDF_DATA,
355 APP_WDF_END => APP_WDF_END,
356 APP_WDF_MASK => APP_WDF_MASK,
357 APP_WDF_WREN => APP_WDF_WREN,
358 APP_RD_DATA => APP_RD_DATA,
359 APP_RD_DATA_END => APP_RD_DATA_END,
360 APP_RD_DATA_VALID => APP_RD_DATA_VALID,
361 APP_RDY => APP_RDY,
362 APP_WDF_RDY => APP_WDF_RDY,
363 APP_SR_REQ => APP_SR_REQ,
364 APP_REF_REQ => APP_REF_REQ,
365 APP_ZQ_REQ => APP_ZQ_REQ,
366 APP_SR_ACTIVE => APP_SR_ACTIVE,
367 APP_REF_ACK => APP_REF_ACK,
368 APP_ZQ_ACK => APP_ZQ_ACK,
369 UI_CLK => CLK,
370 UI_CLK_SYNC_RST => MIG_UI_CLK_SYNC_RST,
371 INIT_CALIB_COMPLETE => MIG_INIT_CALIB_COMPLETE,
372 SYS_CLK_I => CLKMIG,
373 CLK_REF_I => CLKREF,
374 DEVICE_TEMP_I => XADC_TEMP,
375 SYS_RST => MIG_SYS_RST
376 );
377
378 MIG_SYS_RST <= (not LOCKED_CLKMIG) or I_BTN(3); -- provisional !
379
381 generic map ( -- use default INIT_ (LP: Vccint=0.95)
382 CLK_MHZ => sys_conf_clksys_mhz,
384 port map (
385 CLK => CLK,
386 RESET => '0', -- FIXME: no RESET
387 RB_MREQ => RB_MREQ,
389 ALM => open,
390 OT => open,
391 TEMP => XADC_TEMP,
392 VPWRN => A_VPWRN,
393 VPWRP => A_VPWRP
394 );
395
396 UARB : rbd_usracc
397 port map (
398 CLK => CLK,
399 RB_MREQ => RB_MREQ,
401 );
402
403 RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
404 port map (
405 RB_SRES_1 => RB_SRES_TST,
406 RB_SRES_2 => RB_SRES_SYSMON,
407 RB_SRES_3 => RB_SRES_USRACC,
408 RB_SRES_OR => RB_SRES
409 );
410
411 proc_dim: process (CLKMIG)
412 begin
413
414 if rising_edge(CLKMIG) then
415 R_DIMCNT <= slv(unsigned(R_DIMCNT) + 1);
416 if unsigned(R_DIMCNT) = 0 then
417 R_DIMFLG <= '1';
418 else
419 R_DIMFLG <= '0';
420 end if;
421 end if;
422
423 end process proc_dim;
424
425 RB_LAM(0) <= RB_LAM_TST;
426
427 O_LED(1) <= SER_MONI.txact;
428 O_LED(0) <= SER_MONI.rxact;
429
430 -- red LED for serious error conditions
431 O_RGBLED0(0) <= R_DIMFLG and (I_BTN(0) or not LOCKED);
432 O_RGBLED1(0) <= R_DIMFLG and (I_BTN(0));
434 O_RGBLED3(0) <= R_DIMFLG and (I_BTN(0) or not MIG_INIT_CALIB_COMPLETE);
435
436 -- green LED for activity
437 O_RGBLED0(1) <= R_DIMFLG and (I_BTN(1));
438 O_RGBLED1(1) <= R_DIMFLG and (I_BTN(1));
439 O_RGBLED2(1) <= R_DIMFLG and (I_BTN(1) or not APP_RDY);
440 O_RGBLED3(1) <= R_DIMFLG and (I_BTN(1) or not APP_WDF_RDY);
441
442 -- blue LED currently unused
443 O_RGBLED0(2) <= R_DIMFLG and (I_BTN(2));
444 O_RGBLED1(2) <= R_DIMFLG and (I_BTN(2));
445 O_RGBLED2(2) <= R_DIMFLG and (I_BTN(2));
446 O_RGBLED3(2) <= R_DIMFLG and (I_BTN(2));
447
448end syn;
in I std_ulogic
Definition: bufg_unisim.vhd:29
out O std_ulogic
Definition: bufg_unisim.vhd:27
in CLK slbit
Definition: rbd_usracc.vhd:40
in RB_MREQ rb_mreq_type
Definition: rbd_usracc.vhd:41
out RB_SRES rb_sres_type
Definition: rbd_usracc.vhd:43
Definition: rblib.vhd:32
std_logic_vector( 13 downto 0) slv14
Definition: slvtypes.vhd:46
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 11 downto 0) slv12
Definition: slvtypes.vhd:44
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 0 downto 0) slv1
Definition: slvtypes.vhd:33
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
slv16 := x"ffe8" rbaddr_rbmon
slv12 :=( others => '0') XADC_TEMP
slv32 :=( others => '0') DSP_DAT
slbit := '0' MIG_INIT_CALIB_COMPLETE
slv16 := x"0105" sysid_proj
slv16 :=( others => '0') SWI
slv4 :=( others => '0') RB_STAT
rb_sres_type := rb_sres_init RB_SRES_SYSMON
rb_mreq_type := rb_mreq_init RB_MREQ
serport_moni_type := serport_moni_init SER_MONI
slbit := '0' APP_RD_DATA_VALID
slbit := '0' APP_RD_DATA_END
slv( mig_dwidth- 1 downto 0) :=( others => '0') APP_RD_DATA
slv( mig_mawidth- 1 downto 0) :=( others => '0') APP_ADDR
slv2 :=( others => '0') R_DIMCNT
rb_sres_type := rb_sres_init RB_SRES
slv3 :=( others => '0') APP_CMD
slv16 :=( others => '0') LED
slv( mig_mwidth- 1 downto 0) :=( others => '0') APP_WDF_MASK
slbit := '0' MIG_UI_CLK_SYNC_RST
rb_sres_type := rb_sres_init RB_SRES_TST
slv8 :=( others => '0') DSP_DP
slv16 := x"fb00" rbaddr_sysmon
rb_sres_type := rb_sres_init RB_SRES_USRACC
slv16 :=( others => '0') RB_LAM
slv5 :=( others => '0') BTN
slv( mig_dwidth- 1 downto 0) :=( others => '0') APP_WDF_DATA
out DDR3_RESET_N slbit
inout DDR3_DQ slv16
inout DDR3_DQS_P slv2
inout DDR3_DQS_N slv2
in VPWRP slv4 :=( others => '0')
CLK_MHZ integer := 250
RB_ADDR slv16 := x"fb00"
in RB_MREQ rb_mreq_type
out RB_SRES rb_sres_type
in VPWRN slv4 :=( others => '0')
in RESET slbit := '0'
out APP_SR_REQ slbit
Definition: tst_mig.vhd:106
in RESET slbit
Definition: tst_mig.vhd:89
MAWIDTH natural := 28
Definition: tst_mig.vhd:84
in CE_USEC slbit
Definition: tst_mig.vhd:88
MWIDTH natural := 16
Definition: tst_mig.vhd:85
in APP_WDF_RDY slbit
Definition: tst_mig.vhd:105
out APP_WDF_MASK slv( MWIDTH- 1 downto 0)
Definition: tst_mig.vhd:99
out RB_LAM slbit
Definition: tst_mig.vhd:93
in APP_RD_DATA_VALID slbit
Definition: tst_mig.vhd:103
out RB_STAT slv4
Definition: tst_mig.vhd:92
in MIG_INIT_CALIB_COMPLETE slbit
Definition: tst_mig.vhd:113
out APP_WDF_END slbit
Definition: tst_mig.vhd:98
in CLK slbit
Definition: tst_mig.vhd:87
in MIG_UI_CLK_SYNC_RST slbit
Definition: tst_mig.vhd:112
RB_ADDR slv16 := slv( to_unsigned( 2#0000000000000000#, 16) )
Definition: tst_mig.vhd:83
in APP_RD_DATA slv( 8* MWIDTH- 1 downto 0)
Definition: tst_mig.vhd:101
in APP_RDY slbit
Definition: tst_mig.vhd:104
in RB_MREQ rb_mreq_type
Definition: tst_mig.vhd:90
in APP_SR_ACTIVE slbit
Definition: tst_mig.vhd:109
out APP_REF_REQ slbit
Definition: tst_mig.vhd:107
out APP_WDF_WREN slbit
Definition: tst_mig.vhd:100
in MIG_DEVICE_TEMP_I slv12
Definition: tst_mig.vhd:115
in APP_RD_DATA_END slbit
Definition: tst_mig.vhd:102
out APP_ZQ_REQ slbit
Definition: tst_mig.vhd:108
out RB_SRES rb_sres_type
Definition: tst_mig.vhd:91
in APP_ZQ_ACK slbit
Definition: tst_mig.vhd:111
out APP_EN slbit
Definition: tst_mig.vhd:96
out APP_WDF_DATA slv( 8* MWIDTH- 1 downto 0)
Definition: tst_mig.vhd:97
out APP_ADDR slv( MAWIDTH- 1 downto 0)
Definition: tst_mig.vhd:94
in APP_REF_ACK slbit
Definition: tst_mig.vhd:110
out APP_CMD slv3
Definition: tst_mig.vhd:95
Definition: xlib.vhd:35