64use ieee.std_logic_1164.
all;
65use ieee.numeric_std.
all;
136 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
151 signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
157 assert (sys_conf_clksys mod 1000000) = 0
158 report "assert sys_conf_clksys on MHz grid"
169 GEN_TYPE => sys_conf_clksys_gentype
)
179 USECDIV => sys_conf_clksys_mhz,
227 FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
233 CCWIDTH => sys_conf_fx2_ccwidth,
257 end generate FX2_CNTL_IC;
259 FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
265 CCWIDTH => sys_conf_fx2_ccwidth,
294 end generate FX2_CNTL_IC3;
325 SRAM_PROT :
nx_cram_dummy -- connect CRAM
to protection dummy
RXAEMPTY_THRES natural := 1
out MONI fx2ctl_moni_type
TXAFULL_THRES natural := 1
TX2AFULL_THRES natural := 1
RXAEMPTY_THRES natural := 1
out MONI fx2ctl_moni_type
TXAFULL_THRES natural := 1
CLKIN_PERIOD real := 10.0
CLKIN_JITTER real := 0.01
STARTUP_WAIT boolean := false
VCO_MULTIPLY positive := 1
std_logic_vector( 22 downto 0) slv23
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 4 downto 0) slv5
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
out O_LED slv( LWIDTH- 1 downto 0)
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
out SWI slv( SWIDTH- 1 downto 0)
in I_BTN slv( BWIDTH- 1 downto 0)
in I_SWI slv( SWIDTH- 1 downto 0)
out BTN slv( BWIDTH- 1 downto 0)
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
in LED slv( LWIDTH- 1 downto 0)
slv16 :=( others => '0') DSP_DAT
slv8 :=( others => '0') LED
slv16 := x"fef0" rbaddr_hio
fx2ctl_moni_type := fx2ctl_moni_init FX2_MONI
slv8 :=( others => '0') FX2_TXDATA
slv8 :=( others => '0') FX2_RXDATA
slv8 :=( others => '0') SWI
rb_mreq_type := rb_mreq_init RB_MREQ
slbit := '0' FX2_RXAEMPTY
slv8 :=( others => '0') FX2_TX2DATA
slv4 :=( others => '0') DSP_DP
slbit := '0' FX2_TX2AFULL
rb_sres_type := rb_sres_init RB_SRES_HIO
slv5 :=( others => '0') BTN
out RB_MREQ_TOP rb_mreq_type
in RB_SRES_TOP rb_sres_type
in FX2_MONI fx2ctl_moni_type