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W11 CPU core and support modules
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sys_tst_rlink_cuff_n3.vhd
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1-- $Id: sys_tst_rlink_cuff_n3.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_tst_rlink_cuff_n3 - syn
7-- Description: rlink tester design for nexys3 with fx2 interface
8--
9-- Dependencies: vlib/xlib/s6_cmt_sfs
10-- vlib/genlib/clkdivce
11-- bplib/bpgen/bp_rs232_2l4l_iob
12-- bplib/bpgen/sn_humanio_rbus
13-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
14-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
15-- tst_rlink_cuff
16-- bplib/nxcramlib/nx_cram_dummy
17--
18-- Test bench: -
19--
20-- Target Devices: generic
21-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
22--
23-- Synthesized (xst):
24-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
25-- 2014-12-20 614 14.4 131013 xc6slx16-2 1029 1519 104 566 p 9.2 ic2/100
26--
27-- Revision History:
28-- Date Rev Version Comment
29-- 2015-01-25 638 1.2.2 retire fx2_2fifoctl_as
30-- 2014-12-24 620 1.2.1 relocate hio rbus address
31-- 2014-08-15 583 1.2 rb_mreq addr now 16 bit
32-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
33-- 2012-12-29 466 1.0 Initial version; derived from sys_tst_rlink_cuff_n2
34-- and sys_tst_fx2loop_n3
35------------------------------------------------------------------------------
36-- Usage of Nexys 3 Switches, Buttons, LEDs:
37--
38-- SWI(7:3) no function (only connected to sn_humanio_rbus)
39-- (2) 0 -> int/ext RS242 port for rlink
40-- 1 -> use USB interface for rlink
41-- (1) 1 enable XON
42-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
43-- 1 -> Pmod B/top RS232 port /
44--
45-- LED(7) SER_MONI.abact
46-- (6:2) no function (only connected to sn_humanio_rbus)
47-- (1) timer 1 busy
48-- (0) timer 0 busy
49--
50-- DSP: SER_MONI.clkdiv (from auto bauder)
51-- for SWI(2)='0' (serport)
52-- DP(3) not SER_MONI.txok (shows tx back pressure)
53-- (2) SER_MONI.txact (shows tx activity)
54-- (1) not SER_MONI.rxok (shows rx back pressure)
55-- (0) SER_MONI.rxact (shows rx activity)
56-- for SWI(2)='1' (fx2)
57-- DP(3) FX2_TX2BUSY (shows tx2 back pressure)
58-- (2) FX2_TX2ENA(stretched) (shows tx2 activity)
59-- (1) FX2_TXENA(streched) (shows tx activity)
60-- (0) FX2_RXVAL(stretched) (shows rx activity)
61--
62
63library ieee;
64use ieee.std_logic_1164.all;
65use ieee.numeric_std.all;
66
67use work.slvtypes.all;
68use work.xlib.all;
69use work.genlib.all;
70use work.bpgenlib.all;
71use work.bpgenrbuslib.all;
72use work.rblib.all;
73use work.fx2lib.all;
74use work.nxcramlib.all;
75use work.sys_conf.all;
76
77-- ----------------------------------------------------------------------------
78
79entity sys_tst_rlink_cuff_n3 is -- top level
80 -- implements nexys3_fusp_cuff_aif
81 port (
82 I_CLK100 : in slbit; -- 100 MHz clock
83 I_RXD : in slbit; -- receive data (board view)
84 O_TXD : out slbit; -- transmit data (board view)
85 I_SWI : in slv8; -- n3 switches
86 I_BTN : in slv5; -- n3 buttons
87 O_LED : out slv8; -- n3 leds
88 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
89 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
90 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
91 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
92 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
93 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
94 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
95 O_MEM_CLK : out slbit; -- cram: clock
96 O_MEM_CRE : out slbit; -- cram: command register enable
97 I_MEM_WAIT : in slbit; -- cram: mem wait
98 O_MEM_ADDR : out slv23; -- cram: address lines
99 IO_MEM_DATA : inout slv16; -- cram: data lines
100 O_PPCM_CE_N : out slbit; -- ppcm: ...
101 O_PPCM_RST_N : out slbit; -- ppcm: ...
102 O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
103 I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
104 I_FUSP_RXD : in slbit; -- fusp: rs232 rx
105 O_FUSP_TXD : out slbit; -- fusp: rs232 tx
106 I_FX2_IFCLK : in slbit; -- fx2: interface clock
107 O_FX2_FIFO : out slv2; -- fx2: fifo address
108 I_FX2_FLAG : in slv4; -- fx2: fifo flags
109 O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
110 O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
111 O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
112 O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
113 IO_FX2_DATA : inout slv8 -- fx2: data lines
114 );
116
117architecture syn of sys_tst_rlink_cuff_n3 is
118
119 signal CLK : slbit := '0';
120 signal RESET : slbit := '0';
121
122 signal CE_USEC : slbit := '0';
123 signal CE_MSEC : slbit := '0';
124
125 signal RXSD : slbit := '0';
126 signal TXSD : slbit := '0';
127 signal CTS_N : slbit := '0';
128 signal RTS_N : slbit := '0';
129
130 signal SWI : slv8 := (others=>'0');
131 signal BTN : slv5 := (others=>'0');
132 signal LED : slv8 := (others=>'0');
133 signal DSP_DAT : slv16 := (others=>'0');
134 signal DSP_DP : slv4 := (others=>'0');
135
136 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
137 signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
138
139 signal FX2_RXDATA : slv8 := (others=>'0');
140 signal FX2_RXVAL : slbit := '0';
141 signal FX2_RXHOLD : slbit := '0';
142 signal FX2_RXAEMPTY : slbit := '0';
143 signal FX2_TXDATA : slv8 := (others=>'0');
144 signal FX2_TXENA : slbit := '0';
145 signal FX2_TXBUSY : slbit := '0';
146 signal FX2_TXAFULL : slbit := '0';
147 signal FX2_TX2DATA : slv8 := (others=>'0');
148 signal FX2_TX2ENA : slbit := '0';
149 signal FX2_TX2BUSY : slbit := '0';
150 signal FX2_TX2AFULL : slbit := '0';
151 signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
152
153 constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
154
155begin
156
157 assert (sys_conf_clksys mod 1000000) = 0
158 report "assert sys_conf_clksys on MHz grid"
159 severity failure;
160
161 GEN_CLKSYS : s6_cmt_sfs
162 generic map (
163 VCO_DIVIDE => sys_conf_clksys_vcodivide,
164 VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
165 OUT_DIVIDE => sys_conf_clksys_outdivide,
166 CLKIN_PERIOD => 10.0,
167 CLKIN_JITTER => 0.01,
168 STARTUP_WAIT => false,
169 GEN_TYPE => sys_conf_clksys_gentype)
170 port map (
171 CLKIN => I_CLK100,
172 CLKFX => CLK,
173 LOCKED => open
174 );
175
176 CLKDIV : clkdivce
177 generic map (
178 CDUWIDTH => 7, -- good for up to 127 MHz !
179 USECDIV => sys_conf_clksys_mhz,
180 MSECDIV => 1000)
181 port map (
182 CLK => CLK,
183 CE_USEC => CE_USEC,
185 );
186
187 IOB_RS232 : bp_rs232_2l4l_iob
188 port map (
189 CLK => CLK,
190 RESET => '0',
191 SEL => SWI(0),
192 RXD => RXSD,
193 TXD => TXSD,
194 CTS_N => CTS_N,
195 RTS_N => RTS_N,
196 I_RXD0 => I_RXD,
197 O_TXD0 => O_TXD,
202 );
203
204 HIO : sn_humanio_rbus
205 generic map (
206 BWIDTH => 5,
207 DEBOUNCE => sys_conf_hio_debounce,
209 port map (
210 CLK => CLK,
211 RESET => RESET,
212 CE_MSEC => CE_MSEC,
213 RB_MREQ => RB_MREQ,
215 SWI => SWI,
216 BTN => BTN,
217 LED => LED,
218 DSP_DAT => DSP_DAT,
219 DSP_DP => DSP_DP,
220 I_SWI => I_SWI,
221 I_BTN => I_BTN,
222 O_LED => O_LED,
223 O_ANO_N => O_ANO_N,
225 );
226
227 FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
228 CNTL : fx2_2fifoctl_ic
229 generic map (
230 RXFAWIDTH => 5,
231 TXFAWIDTH => 5,
232 PETOWIDTH => sys_conf_fx2_petowidth,
233 CCWIDTH => sys_conf_fx2_ccwidth,
234 RXAEMPTY_THRES => 1,
235 TXAFULL_THRES => 1)
236 port map (
237 CLK => CLK,
238 RESET => RESET,
240 RXVAL => FX2_RXVAL,
244 TXENA => FX2_TXENA,
247 MONI => FX2_MONI,
256 );
257 end generate FX2_CNTL_IC;
258
259 FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
260 CNTL : fx2_3fifoctl_ic
261 generic map (
262 RXFAWIDTH => 5,
263 TXFAWIDTH => 5,
264 PETOWIDTH => sys_conf_fx2_petowidth,
265 CCWIDTH => sys_conf_fx2_ccwidth,
266 RXAEMPTY_THRES => 1,
267 TXAFULL_THRES => 1,
268 TX2AFULL_THRES => 1)
269 port map (
270 CLK => CLK,
271 RESET => RESET,
273 RXVAL => FX2_RXVAL,
277 TXENA => FX2_TXENA,
284 MONI => FX2_MONI,
293 );
294 end generate FX2_CNTL_IC3;
295
296 TST : entity work.tst_rlink_cuff
297 port map (
298 CLK => CLK,
299 RESET => '0',
300 CE_USEC => CE_USEC,
301 CE_MSEC => CE_MSEC,
304 SWI => SWI,
305 BTN => BTN(3 downto 0),
306 LED => LED,
307 DSP_DAT => DSP_DAT,
308 DSP_DP => DSP_DP,
309 RXSD => RXSD,
310 TXSD => TXSD,
311 RTS_N => RTS_N,
312 CTS_N => CTS_N,
323 );
324
325 SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
326 port map (
327 O_MEM_CE_N => O_MEM_CE_N,
328 O_MEM_BE_N => O_MEM_BE_N,
329 O_MEM_WE_N => O_MEM_WE_N,
330 O_MEM_OE_N => O_MEM_OE_N,
331 O_MEM_ADV_N => O_MEM_ADV_N,
332 O_MEM_CLK => O_MEM_CLK,
333 O_MEM_CRE => O_MEM_CRE,
334 I_MEM_WAIT => I_MEM_WAIT,
335 O_MEM_ADDR => O_MEM_ADDR,
336 IO_MEM_DATA => IO_MEM_DATA
337 );
338
339 O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
340 O_PPCM_RST_N <= '1'; --
341
342end syn;
343
in RESET slbit := '0'
out CE_MSEC slbit
Definition: clkdivce.vhd:39
USECDIV positive := 50
Definition: clkdivce.vhd:33
CDUWIDTH positive := 6
Definition: clkdivce.vhd:32
out CE_USEC slbit
Definition: clkdivce.vhd:37
MSECDIV positive := 1000
Definition: clkdivce.vhd:34
in CLK slbit
Definition: clkdivce.vhd:36
inout IO_FX2_DATA slv8
in I_FX2_IFCLK slbit
out O_FX2_PKTEND_N slbit
out TXAFULL slbit
RXAEMPTY_THRES natural := 1
CCWIDTH positive := 5
out O_FX2_SLWR_N slbit
out O_FX2_FIFO slv2
PETOWIDTH positive := 7
TXFAWIDTH positive := 5
RXFAWIDTH positive := 5
out MONI fx2ctl_moni_type
out RXAEMPTY slbit
in RESET slbit := '0'
TXAFULL_THRES natural := 1
out O_FX2_SLRD_N slbit
out O_FX2_SLOE_N slbit
inout IO_FX2_DATA slv8
TX2AFULL_THRES natural := 1
in I_FX2_IFCLK slbit
out TX2AFULL slbit
out O_FX2_PKTEND_N slbit
out TXAFULL slbit
out TX2BUSY slbit
RXAEMPTY_THRES natural := 1
CCWIDTH positive := 5
out O_FX2_SLWR_N slbit
out O_FX2_FIFO slv2
PETOWIDTH positive := 7
TXFAWIDTH positive := 5
RXFAWIDTH positive := 5
out MONI fx2ctl_moni_type
out RXAEMPTY slbit
in RESET slbit := '0'
TXAFULL_THRES natural := 1
out O_FX2_SLRD_N slbit
out O_FX2_SLOE_N slbit
Definition: rblib.vhd:32
VCO_DIVIDE positive := 1
GEN_TYPE string := "PLL"
CLKIN_PERIOD real := 10.0
OUT_DIVIDE positive := 1
in CLKIN slbit
CLKIN_JITTER real := 0.01
STARTUP_WAIT boolean := false
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
std_logic_vector( 22 downto 0) slv23
Definition: slvtypes.vhd:56
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
DEBOUNCE boolean := true
out O_LED slv( LWIDTH- 1 downto 0)
RB_ADDR slv16 := x"fef0"
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
out SWI slv( SWIDTH- 1 downto 0)
in I_BTN slv( BWIDTH- 1 downto 0)
in I_SWI slv( SWIDTH- 1 downto 0)
out BTN slv( BWIDTH- 1 downto 0)
in RB_MREQ rb_mreq_type
BWIDTH positive := 4
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
out RB_SRES rb_sres_type
in LED slv( LWIDTH- 1 downto 0)
in RESET slbit := '0'
Definition: xlib.vhd:35