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W11 CPU core and support modules
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sys_tst_serloop1_n3.vhd
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1-- $Id: sys_tst_serloop1_n3.vhd 1369 2023-02-08 18:59:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_tst_serloop1_n3 - syn
7-- Description: Serial link tester design for nexys3 (serport_1clock case)
8--
9-- Dependencies: genlib/clkdivce
10-- bpgen/bp_rs232_2l4l_iob
11-- bpgen/sn_humanio
12-- tst_serloop_hiomap
13-- vlib/serport/serport_1clock
14-- tst_serloop
15-- vlib/nxcramlib/nx_cram_dummy
16--
17-- Test bench: -
18--
19-- Target Devices: generic
20-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
21--
22-- Synthesized (xst):
23-- Date Rev ise Target flop lutl lutm slic t peri
24-- 2011-12-11 438 13.1 O40d xc6slx16-2 419 650 32 221 t 7.7
25--
26-- Revision History:
27-- Date Rev Version Comment
28-- 2011-12-11 438 1.0 Initial version (derived from sys_tst_serloop_n3)
29------------------------------------------------------------------------------
30--
31
32library ieee;
33use ieee.std_logic_1164.all;
34use ieee.numeric_std.all;
35
36use work.slvtypes.all;
37use work.xlib.all;
38use work.genlib.all;
39use work.bpgenlib.all;
40use work.tst_serlooplib.all;
41use work.serportlib.all;
42use work.nxcramlib.all;
43use work.sys_conf.all;
44
45-- ----------------------------------------------------------------------------
46
47entity sys_tst_serloop1_n3 is -- top level
48 -- implements nexys3_fusp_aif
49 port (
50 I_CLK100 : in slbit; -- 100 MHz clock
51 I_RXD : in slbit; -- receive data (board view)
52 O_TXD : out slbit; -- transmit data (board view)
53 I_SWI : in slv8; -- n3 switches
54 I_BTN : in slv5; -- n3 buttons
55 O_LED : out slv8; -- n3 leds
56 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
57 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
58 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
59 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
60 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
61 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
62 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
63 O_MEM_CLK : out slbit; -- cram: clock
64 O_MEM_CRE : out slbit; -- cram: command register enable
65 I_MEM_WAIT : in slbit; -- cram: mem wait
66 O_MEM_ADDR : out slv23; -- cram: address lines
67 IO_MEM_DATA : inout slv16; -- cram: data lines
68 O_PPCM_CE_N : out slbit; -- ppcm: ...
69 O_PPCM_RST_N : out slbit; -- ppcm: ...
70 O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
71 I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
72 I_FUSP_RXD : in slbit; -- fusp: rs232 rx
73 O_FUSP_TXD : out slbit -- fusp: rs232 tx
74 );
76
77architecture syn of sys_tst_serloop1_n3 is
78
79 signal CLK : slbit := '0';
80 signal RESET : slbit := '0';
81
82 signal CE_USEC : slbit := '0';
83 signal CE_MSEC : slbit := '0';
84
85 signal RXD : slbit := '0';
86 signal TXD : slbit := '0';
87 signal CTS_N : slbit := '0';
88 signal RTS_N : slbit := '0';
89
90 signal SWI : slv8 := (others=>'0');
91 signal BTN : slv5 := (others=>'0');
92 signal LED : slv8 := (others=>'0');
93 signal DSP_DAT : slv16 := (others=>'0');
94 signal DSP_DP : slv4 := (others=>'0');
95
96 signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
97 signal HIO_STAT : hio_stat_type := hio_stat_init;
98
99 signal RXDATA : slv8 := (others=>'0');
100 signal RXVAL : slbit := '0';
101 signal RXHOLD : slbit := '0';
102 signal TXDATA : slv8 := (others=>'0');
103 signal TXENA : slbit := '0';
104 signal TXBUSY : slbit := '0';
105
106 signal SER_MONI : serport_moni_type := serport_moni_init;
107
108begin
109
110 CLK <= I_CLK100;
111
112 CLKDIV : clkdivce
113 generic map (
114 CDUWIDTH => 8,
115 USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20
116 MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
117 port map (
118 CLK => CLK,
119 CE_USEC => open,
121 );
122
123 HIO : sn_humanio
124 generic map (
125 BWIDTH => 5,
126 DEBOUNCE => sys_conf_hio_debounce)
127 port map (
128 CLK => CLK,
129 RESET => '0',
130 CE_MSEC => CE_MSEC,
131 SWI => SWI,
132 BTN => BTN,
133 LED => LED,
134 DSP_DAT => DSP_DAT,
135 DSP_DP => DSP_DP,
136 I_SWI => I_SWI,
137 I_BTN => I_BTN,
138 O_LED => O_LED,
139 O_ANO_N => O_ANO_N,
141 );
142
143 RESET <= BTN(0); -- BTN(0) will reset tester !!
144
145 HIOMAP : tst_serloop_hiomap
146 port map (
147 CLK => CLK,
148 RESET => RESET,
152 SWI => SWI,
153 BTN => BTN(3 downto 0),
154 LED => LED,
155 DSP_DAT => DSP_DAT,
156 DSP_DP => DSP_DP
157 );
158
159 IOB_RS232 : bp_rs232_2l4l_iob
160 port map (
161 CLK => CLK,
162 RESET => '0',
163 SEL => SWI(0), -- port selection
164 RXD => RXD,
165 TXD => TXD,
166 CTS_N => CTS_N,
167 RTS_N => RTS_N,
168 I_RXD0 => I_RXD,
169 O_TXD0 => O_TXD,
174 );
175
176 SERPORT : serport_1clock
177 generic map (
178 CDWIDTH => 15,
179 CDINIT => sys_conf_uart_cdinit,
180 RXFAWIDTH => 5,
181 TXFAWIDTH => 5)
182 port map (
183 CLK => CLK,
184 CE_MSEC => CE_MSEC,
185 RESET => RESET,
186 ENAXON => HIO_CNTL.enaxon,
187 ENAESC => HIO_CNTL.enaesc,
188 RXDATA => RXDATA,
189 RXVAL => RXVAL,
190 RXHOLD => RXHOLD,
191 TXDATA => TXDATA,
192 TXENA => TXENA,
193 TXBUSY => TXBUSY,
194 MONI => SER_MONI,
195 RXSD => RXD,
196 TXSD => TXD,
197 RXRTS_N => RTS_N,
198 TXCTS_N => CTS_N
199 );
200
201 TESTER : tst_serloop
202 port map (
203 CLK => CLK,
204 RESET => RESET,
205 CE_MSEC => CE_MSEC,
209 RXDATA => RXDATA,
210 RXVAL => RXVAL,
211 RXHOLD => RXHOLD,
212 TXDATA => TXDATA,
213 TXENA => TXENA,
214 TXBUSY => TXBUSY
215 );
216
217 SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
218 port map (
219 O_MEM_CE_N => O_MEM_CE_N,
220 O_MEM_BE_N => O_MEM_BE_N,
221 O_MEM_WE_N => O_MEM_WE_N,
222 O_MEM_OE_N => O_MEM_OE_N,
223 O_MEM_ADV_N => O_MEM_ADV_N,
224 O_MEM_CLK => O_MEM_CLK,
225 O_MEM_CRE => O_MEM_CRE,
226 I_MEM_WAIT => I_MEM_WAIT,
227 O_MEM_ADDR => O_MEM_ADDR,
228 IO_MEM_DATA => IO_MEM_DATA
229 );
230
231 O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
232 O_PPCM_RST_N <= '1'; --
233
234end syn;
in RESET slbit := '0'
out CE_MSEC slbit
Definition: clkdivce.vhd:39
USECDIV positive := 50
Definition: clkdivce.vhd:33
CDUWIDTH positive := 6
Definition: clkdivce.vhd:32
out CE_USEC slbit
Definition: clkdivce.vhd:37
MSECDIV positive := 1000
Definition: clkdivce.vhd:34
in CLK slbit
Definition: clkdivce.vhd:36
TXFAWIDTH natural := 5
CDWIDTH positive := 13
in ENAESC slbit
in ENAXON slbit
in TXCTS_N slbit
RXFAWIDTH natural := 5
CDINIT natural := 15
out RXRTS_N slbit
out MONI serport_moni_type
out RXDATA slv8
out RXVAL slbit
out TXSD slbit
in RXHOLD slbit
in CE_MSEC slbit
out TXBUSY slbit
std_logic_vector( 22 downto 0) slv23
Definition: slvtypes.vhd:56
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:63
DEBOUNCE boolean := true
Definition: sn_humanio.vhd:54
out O_LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:66
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:62
out SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:59
in I_BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:65
in I_SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:64
out O_SEG_N slv8
Definition: sn_humanio.vhd:69
out BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:60
in CLK slbit
Definition: sn_humanio.vhd:56
BWIDTH positive := 4
Definition: sn_humanio.vhd:51
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:67
in LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:61
in RESET slbit := '0'
Definition: sn_humanio.vhd:57
in CE_MSEC slbit
Definition: sn_humanio.vhd:58
slv16 :=( others => '0') DSP_DAT
slv8 :=( others => '0') LED
hio_cntl_type := hio_cntl_init HIO_CNTL
slv8 :=( others => '0') SWI
serport_moni_type := serport_moni_init SER_MONI
slv8 :=( others => '0') RXDATA
hio_stat_type := hio_stat_init HIO_STAT
slv4 :=( others => '0') DSP_DP
slv5 :=( others => '0') BTN
slv8 :=( others => '0') TXDATA
in HIO_STAT hio_stat_type
in SER_MONI serport_moni_type
out HIO_CNTL hio_cntl_type
in TXBUSY slbit
Definition: tst_serloop.vhd:48
in RESET slbit
Definition: tst_serloop.vhd:37
in RXDATA slv8
Definition: tst_serloop.vhd:42
in SER_MONI serport_moni_type
Definition: tst_serloop.vhd:41
out TXDATA slv8
Definition: tst_serloop.vhd:45
in CLK slbit
Definition: tst_serloop.vhd:36
out HIO_STAT hio_stat_type
Definition: tst_serloop.vhd:40
out RXHOLD slbit
Definition: tst_serloop.vhd:44
in RXVAL slbit
Definition: tst_serloop.vhd:43
in HIO_CNTL hio_cntl_type
Definition: tst_serloop.vhd:39
out TXENA slbit
Definition: tst_serloop.vhd:46
in CE_MSEC slbit
Definition: tst_serloop.vhd:38
Definition: xlib.vhd:35