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W11 CPU core and support modules
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sys_tst_serloop2_n2.vhd
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1-- $Id: sys_tst_serloop2_n2.vhd 1369 2023-02-08 18:59:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_tst_serloop2_n2 - syn
7-- Description: Serial link tester design for nexys2 (serport_2clock case)
8--
9-- Dependencies: vlib/xlib/dcm_sfs
10-- genlib/clkdivce
11-- bpgen/bp_rs232_2l4l_iob
12-- bpgen/sn_humanio
13-- tst_serloop_hiomap
14-- vlib/serport/serport_2clock
15-- tst_serloop
16-- vlib/nxcramlib/nx_cram_dummy
17--
18-- Test bench: -
19--
20-- Target Devices: generic
21-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
22--
23-- Synthesized (xst):
24-- Date Rev ise Target flop lutl lutm slic t peri
25-- 2011-12-16 439 13.1 O40d xc3s1200e-4 516 696 64 575 t xx.x
26-- 2011-11-16 426 13.1 O40d xc3s1200e-4 494 661 64 547 t xx.x
27-- 2011-11-13 425 13.1 O40d xc3s1200e-4 487 645 64 532 t xx.x
28--
29-- Revision History:
30-- Date Rev Version Comment
31-- 2011-12-23 444 1.1 remove clksys output hack
32-- 2011-12-09 437 1.0.4 rename serport stat->moni port
33-- 2011-11-26 433 1.0.3 use nx_cram_dummy now
34-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage
35-- 2011-11-17 426 1.0.1 use dcm_sfs now
36-- 2011-11-12 423 1.0 Initial version
37-- 2011-11-09 422 0.5 First draft
38------------------------------------------------------------------------------
39--
40
41library ieee;
42use ieee.std_logic_1164.all;
43use ieee.numeric_std.all;
44
45use work.slvtypes.all;
46use work.xlib.all;
47use work.genlib.all;
48use work.bpgenlib.all;
49use work.tst_serlooplib.all;
50use work.serportlib.all;
51use work.nxcramlib.all;
52use work.sys_conf.all;
53
54-- ----------------------------------------------------------------------------
55
56entity sys_tst_serloop2_n2 is -- top level
57 -- implements nexys2_fusp_aif
58 port (
59 I_CLK50 : in slbit; -- 50 MHz clock
60 I_RXD : in slbit; -- receive data (board view)
61 O_TXD : out slbit; -- transmit data (board view)
62 I_SWI : in slv8; -- n2 switches
63 I_BTN : in slv4; -- n2 buttons
64 O_LED : out slv8; -- n2 leds
65 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
66 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
67 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
68 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
69 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
70 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
71 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
72 O_MEM_CLK : out slbit; -- cram: clock
73 O_MEM_CRE : out slbit; -- cram: command register enable
74 I_MEM_WAIT : in slbit; -- cram: mem wait
75 O_MEM_ADDR : out slv23; -- cram: address lines
76 IO_MEM_DATA : inout slv16; -- cram: data lines
77 O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
78 O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
79 I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
80 I_FUSP_RXD : in slbit; -- fusp: rs232 rx
81 O_FUSP_TXD : out slbit -- fusp: rs232 tx
82 );
84
85architecture syn of sys_tst_serloop2_n2 is
86
87 signal CLK : slbit := '0';
88 signal RESET : slbit := '0';
89
90 signal CE_USEC : slbit := '0';
91 signal CE_MSEC : slbit := '0';
92
93 signal CLKS : slbit := '0';
94 signal CES_MSEC : slbit := '0';
95
96 signal RXD : slbit := '0';
97 signal TXD : slbit := '0';
98 signal CTS_N : slbit := '0';
99 signal RTS_N : slbit := '0';
100
101 signal SWI : slv8 := (others=>'0');
102 signal BTN : slv4 := (others=>'0');
103 signal LED : slv8 := (others=>'0');
104 signal DSP_DAT : slv16 := (others=>'0');
105 signal DSP_DP : slv4 := (others=>'0');
106
107 signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
108 signal HIO_STAT : hio_stat_type := hio_stat_init;
109
110 signal RXDATA : slv8 := (others=>'0');
111 signal RXVAL : slbit := '0';
112 signal RXHOLD : slbit := '0';
113 signal TXDATA : slv8 := (others=>'0');
114 signal TXENA : slbit := '0';
115 signal TXBUSY : slbit := '0';
116
117 signal SER_MONI : serport_moni_type := serport_moni_init;
118
119begin
120
121 DCM_U : dcm_sfs
122 generic map (
123 CLKFX_DIVIDE => 2,
124 CLKFX_MULTIPLY => 4,
125 CLKIN_PERIOD => 20.0)
126 port map (
127 CLKIN => I_CLK50,
128 CLKFX => CLK,
129 LOCKED => open
130 );
131
132 CLKDIV_U : clkdivce
133 generic map (
134 CDUWIDTH => 7,
135 USECDIV => sys_conf_clkudiv_usecdiv, -- syn: 100 sim: 20
136 MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
137 port map (
138 CLK => CLK,
139 CE_USEC => open,
141 );
142
143 DCM_S : dcm_sfs
144 generic map (
145 CLKFX_DIVIDE => 5,
146 CLKFX_MULTIPLY => 6,
147 CLKIN_PERIOD => 20.0)
148 port map (
149 CLKIN => I_CLK50,
150 CLKFX => CLKS,
151 LOCKED => open
152 );
153
154 CLKDIV_S : clkdivce
155 generic map (
156 CDUWIDTH => 6,
157 USECDIV => sys_conf_clksdiv_usecdiv, -- syn: 60 sim: 12
158 MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
159 port map (
160 CLK => CLKS,
161 CE_USEC => open,
163 );
164
165 HIO : sn_humanio
166 generic map (
167 DEBOUNCE => sys_conf_hio_debounce)
168 port map (
169 CLK => CLK,
170 RESET => '0',
171 CE_MSEC => CE_MSEC,
172 SWI => SWI,
173 BTN => BTN,
174 LED => LED,
175 DSP_DAT => DSP_DAT,
176 DSP_DP => DSP_DP,
177 I_SWI => I_SWI,
178 I_BTN => I_BTN,
179 O_LED => O_LED,
180 O_ANO_N => O_ANO_N,
182 );
183
184 RESET <= BTN(0); -- BTN(0) will reset tester !!
185
186 HIOMAP : tst_serloop_hiomap
187 port map (
188 CLK => CLK,
189 RESET => RESET,
193 SWI => SWI,
194 BTN => BTN,
195 LED => LED,
196 DSP_DAT => DSP_DAT,
197 DSP_DP => DSP_DP
198 );
199
200 IOB_RS232 : bp_rs232_2l4l_iob
201 port map (
202 CLK => CLKS,
203 RESET => '0',
204 SEL => SWI(0), -- port selection
205 RXD => RXD,
206 TXD => TXD,
207 CTS_N => CTS_N,
208 RTS_N => RTS_N,
209 I_RXD0 => I_RXD,
210 O_TXD0 => O_TXD,
215 );
216
217 SERPORT : serport_2clock
218 generic map (
219 CDWIDTH => 15,
220 CDINIT => sys_conf_uart_cdinit,
221 RXFAWIDTH => 5,
222 TXFAWIDTH => 5)
223 port map (
224 CLKU => CLK,
225 RESET => RESET,
226 CLKS => CLKS,
228 ENAXON => HIO_CNTL.enaxon,
229 ENAESC => HIO_CNTL.enaesc,
230 RXDATA => RXDATA,
231 RXVAL => RXVAL,
232 RXHOLD => RXHOLD,
233 TXDATA => TXDATA,
234 TXENA => TXENA,
235 TXBUSY => TXBUSY,
236 MONI => SER_MONI,
237 RXSD => RXD,
238 TXSD => TXD,
239 RXRTS_N => RTS_N,
240 TXCTS_N => CTS_N
241 );
242
243 TESTER : tst_serloop
244 port map (
245 CLK => CLK,
246 RESET => RESET,
247 CE_MSEC => CE_MSEC,
251 RXDATA => RXDATA,
252 RXVAL => RXVAL,
253 RXHOLD => RXHOLD,
254 TXDATA => TXDATA,
255 TXENA => TXENA,
256 TXBUSY => TXBUSY
257 );
258
259 SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
260 port map (
261 O_MEM_CE_N => O_MEM_CE_N,
262 O_MEM_BE_N => O_MEM_BE_N,
263 O_MEM_WE_N => O_MEM_WE_N,
264 O_MEM_OE_N => O_MEM_OE_N,
265 O_MEM_ADV_N => O_MEM_ADV_N,
266 O_MEM_CLK => O_MEM_CLK,
267 O_MEM_CRE => O_MEM_CRE,
268 I_MEM_WAIT => I_MEM_WAIT,
269 O_MEM_ADDR => O_MEM_ADDR,
270 IO_MEM_DATA => IO_MEM_DATA
271 );
272
273 O_FLA_CE_N <= '1'; -- keep Flash memory disabled
274
275end syn;
in RESET slbit := '0'
out CE_MSEC slbit
Definition: clkdivce.vhd:39
USECDIV positive := 50
Definition: clkdivce.vhd:33
CDUWIDTH positive := 6
Definition: clkdivce.vhd:32
out CE_USEC slbit
Definition: clkdivce.vhd:37
MSECDIV positive := 1000
Definition: clkdivce.vhd:34
in CLK slbit
Definition: clkdivce.vhd:36
CLKFX_DIVIDE positive := 1
in CLKIN slbit
CLKFX_MULTIPLY positive := 1
out LOCKED slbit
CLKIN_PERIOD real := 20.0
out CLKFX slbit
TXFAWIDTH natural := 5
CDWIDTH positive := 13
in ENAESC slbit
in ENAXON slbit
in TXCTS_N slbit
RXFAWIDTH natural := 5
CDINIT natural := 15
out RXRTS_N slbit
out MONI serport_moni_type
out RXDATA slv8
out RXVAL slbit
out TXSD slbit
in RXHOLD slbit
out TXBUSY slbit
in CES_MSEC slbit
std_logic_vector( 22 downto 0) slv23
Definition: slvtypes.vhd:56
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:63
DEBOUNCE boolean := true
Definition: sn_humanio.vhd:54
out O_LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:66
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:62
out SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:59
in I_BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:65
in I_SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:64
out O_SEG_N slv8
Definition: sn_humanio.vhd:69
out BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:60
in CLK slbit
Definition: sn_humanio.vhd:56
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:67
in LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:61
in RESET slbit := '0'
Definition: sn_humanio.vhd:57
in CE_MSEC slbit
Definition: sn_humanio.vhd:58
slv16 :=( others => '0') DSP_DAT
slv8 :=( others => '0') LED
hio_cntl_type := hio_cntl_init HIO_CNTL
slv8 :=( others => '0') SWI
serport_moni_type := serport_moni_init SER_MONI
slv8 :=( others => '0') RXDATA
hio_stat_type := hio_stat_init HIO_STAT
slv4 :=( others => '0') DSP_DP
slv4 :=( others => '0') BTN
slv8 :=( others => '0') TXDATA
in HIO_STAT hio_stat_type
in SER_MONI serport_moni_type
out HIO_CNTL hio_cntl_type
in TXBUSY slbit
Definition: tst_serloop.vhd:48
in RESET slbit
Definition: tst_serloop.vhd:37
in RXDATA slv8
Definition: tst_serloop.vhd:42
in SER_MONI serport_moni_type
Definition: tst_serloop.vhd:41
out TXDATA slv8
Definition: tst_serloop.vhd:45
in CLK slbit
Definition: tst_serloop.vhd:36
out HIO_STAT hio_stat_type
Definition: tst_serloop.vhd:40
out RXHOLD slbit
Definition: tst_serloop.vhd:44
in RXVAL slbit
Definition: tst_serloop.vhd:43
in HIO_CNTL hio_cntl_type
Definition: tst_serloop.vhd:39
out TXENA slbit
Definition: tst_serloop.vhd:46
in CE_MSEC slbit
Definition: tst_serloop.vhd:38
Definition: xlib.vhd:35