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W11 CPU core and support modules
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sys_tst_sram_n4d.vhd
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1-- $Id: sys_tst_sram_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2018-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_tst_sram_n4d - syn
7-- Description: test of nexys4d ddr and its mig controller
8--
9-- Dependencies: vlib/xlib/bufg_unisim
10-- bplib/bpgen/s7_cmt_1ce1ce2c
11-- cdclib/cdc_signal_s1_as
12-- bplib/bpgen/bp_rs232_4line_iob
13-- bplib/bpgen/sn_humanio
14-- vlib/rlink/rlink_sp2c
15-- tst_sram
16-- bplib/nexyx4d/sramif_mig_nexys4d
17-- bplib/sysmon/sysmonx_rbus_base
18-- vlib/rbus/rbd_usracc
19-- vlib/rbus/rb_sres_or_3
20--
21-- Test bench: tb/tb_tst_sram_n4d
22--
23-- Target Devices: generic
24-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0
25--
26-- Synthesized:
27-- Date Rev viv Target flop lutl lutm bram slic
28-- 2022-07-05 1247 2022.1 xc7a100t-1 4408 4197 608 5 1761
29-- 2019-08-10 1201 2019.1 xc7a100t-1 4409 4606 656 5 1875
30-- 2019-02-02 1108 2018.3 xc7a100t-1 4408 4606 656 5 1895
31-- 2019-02-02 1108 2017.2 xc7a100t-1 4403 4900 657 5 1983
32-- 2019-01-02 1101 2017.2 xc7a100t-1 4403 4900 640 5 1983
33--
34-- Revision History:
35-- Date Rev Version Comment
36-- 2022-07-05 1247 1.1.1 use bufg_unisim
37-- 2019-08-10 1201 1.1 use 100 MHz MIG SYS_CLK
38-- 2019-01-02 1101 1.0 Initial version
39-- 2018-12-30 1099 0.1 First draft (derived from sys_tst_sram_n4/arty)
40------------------------------------------------------------------------------
41
42library ieee;
43use ieee.std_logic_1164.all;
44use ieee.numeric_std.all;
45
46use work.slvtypes.all;
47use work.xlib.all;
48use work.cdclib.all;
49use work.serportlib.all;
50use work.rblib.all;
51use work.rbdlib.all;
52use work.rlinklib.all;
53use work.bpgenlib.all;
54use work.sysmonrbuslib.all;
55use work.s3boardlib.all;
56use work.miglib.all;
57use work.miglib_nexys4d.all;
58use work.sys_conf.all;
59
60-- ----------------------------------------------------------------------------
61
62entity sys_tst_sram_n4d is -- top level
63 -- implements nexys4d_mig_aif
64 port (
65 I_CLK100 : in slbit; -- 100 MHz clock
66 I_RXD : in slbit; -- receive data (board view)
67 O_TXD : out slbit; -- transmit data (board view)
68 O_RTS_N : out slbit; -- rx rts (board view; act.low)
69 I_CTS_N : in slbit; -- tx cts (board view; act.low)
70 I_SWI : in slv16; -- n4 switches
71 I_BTN : in slv5; -- n4 buttons
72 I_BTNRST_N : in slbit; -- n4 reset button
73 O_LED : out slv16; -- n4 leds
74 O_RGBLED0 : out slv3; -- n4 rgb-led 0
75 O_RGBLED1 : out slv3; -- n4 rgb-led 1
76 O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
77 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
78 DDR2_DQ : inout slv16; -- dram: data in/out
79 DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p)
80 DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n)
81 DDR2_ADDR : out slv13; -- dram: address
82 DDR2_BA : out slv3; -- dram: bank address
83 DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low)
84 DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low)
85 DDR2_WE_N : out slbit; -- dram: write enable (act.low)
86 DDR2_CK_P : out slv1; -- dram: clock (diff-p)
87 DDR2_CK_N : out slv1; -- dram: clock (diff-n)
88 DDR2_CKE : out slv1; -- dram: clock enable
89 DDR2_CS_N : out slv1; -- dram: chip select (act.low)
90 DDR2_DM : out slv2; -- dram: data input mask
91 DDR2_ODT : out slv1 -- dram: on-die termination
92 );
94
95architecture syn of sys_tst_sram_n4d is
96
97 signal CLK100_BUF : slbit := '0';
98
99 signal CLK : slbit := '0';
100 signal CE_USEC : slbit := '0';
101 signal CE_MSEC : slbit := '0';
102
103 signal CLKS : slbit := '0';
104 signal CES_MSEC : slbit := '0';
105
106 signal CLKREF : slbit := '0';
107
108 signal LOCKED : slbit := '0'; -- raw LOCKED
109 signal LOCKED_CLKMIG : slbit := '0'; -- sync'ed to CLKMIG
110
111 signal GBL_RESET : slbit := '0';
112 signal MEM_RESET : slbit := '0';
113 signal MEM_RESET_RRI : slbit := '0';
114
115 signal RXD : slbit := '1';
116 signal TXD : slbit := '0';
117 signal CTS_N : slbit := '0';
118 signal RTS_N : slbit := '0';
119
120 signal SWI : slv16 := (others=>'0');
121 signal BTN : slv5 := (others=>'0');
122 signal LED : slv16 := (others=>'0');
123 signal DSP_DAT : slv32 := (others=>'0');
124 signal DSP_DP : slv8 := (others=>'0');
125
126 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
127 signal RB_SRES : rb_sres_type := rb_sres_init;
128 signal RB_LAM : slv16 := (others=>'0');
129 signal RB_STAT : slv4 := (others=>'0');
130
131 signal SER_MONI : serport_moni_type := serport_moni_init;
132
133 signal RB_SRES_TST : rb_sres_type := rb_sres_init;
134 signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
135 signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
136
137 signal RB_LAM_TST : slbit := '0';
138
139 signal MEM_REQ : slbit := '0';
140 signal MEM_WE : slbit := '0';
141 signal MEM_BUSY : slbit := '0';
142 signal MEM_ACK_R : slbit := '0';
143 signal MEM_ACK_W : slbit := '0';
144 signal MEM_ACT_R : slbit := '0';
145 signal MEM_ACT_W : slbit := '0';
146 signal MEM_ADDR : slv20 := (others=>'0');
147 signal MEM_BE : slv4 := (others=>'0');
148 signal MEM_DI : slv32 := (others=>'0');
149 signal MEM_DO : slv32 := (others=>'0');
150
151 signal MIG_MONI : sramif2migui_moni_type := sramif2migui_moni_init;
152 signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
153
154 constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
155
156 constant sysid_proj : slv16 := x"0104"; -- tst_sram
157 constant sysid_board : slv8 := x"08"; -- nexys4d
158 constant sysid_vers : slv8 := x"00";
159
160begin
161
162 CLK100_BUFG: bufg_unisim
163 port map (
164 I => I_CLK100,
165 O => CLK100_BUF
166 );
167
168 GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
169 generic map (
170 CLKIN_PERIOD => 10.0,
171 CLKIN_JITTER => 0.01,
172 STARTUP_WAIT => false,
173 CLK0_VCODIV => sys_conf_clksys_vcodivide,
174 CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
175 CLK0_OUTDIV => sys_conf_clksys_outdivide,
176 CLK0_GENTYPE => sys_conf_clksys_gentype,
177 CLK0_CDUWIDTH => 7,
178 CLK0_USECDIV => sys_conf_clksys_mhz,
179 CLK0_MSECDIV => 1000,
180 CLK1_VCODIV => sys_conf_clkser_vcodivide,
181 CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
182 CLK1_OUTDIV => sys_conf_clkser_outdivide,
183 CLK1_GENTYPE => sys_conf_clkser_gentype,
184 CLK1_CDUWIDTH => 7,
185 CLK1_USECDIV => sys_conf_clkser_mhz,
186 CLK1_MSECDIV => 1000,
187 CLK23_VCODIV => 1,
188 CLK23_VCOMUL => 12, -- vco 1200 MHz
189 CLK2_OUTDIV => 12, -- mig sys 100.0 MHz (unused)
190 CLK3_OUTDIV => 6, -- mig ref 200.0 MHz
191 CLK23_GENTYPE => "PLL")
192 port map (
193 CLKIN => CLK100_BUF,
194 CLK0 => CLK,
195 CE0_USEC => CE_USEC,
196 CE0_MSEC => CE_MSEC,
197 CLK1 => CLKS,
198 CE1_USEC => open,
199 CE1_MSEC => CES_MSEC,
200 CLK2 => open,
201 CLK3 => CLKREF,
202 LOCKED => LOCKED
203 );
204
205 CDC_CLKMIG_LOCKED : cdc_signal_s1_as
206 port map (
207 CLKO => CLK100_BUF,
208 DI => LOCKED,
210 );
211
212 IOB_RS232 : bp_rs232_4line_iob
213 port map (
214 CLK => CLKS,
215 RXD => RXD,
216 TXD => TXD,
217 CTS_N => CTS_N,
218 RTS_N => RTS_N,
219 I_RXD => I_RXD,
220 O_TXD => O_TXD,
221 I_CTS_N => I_CTS_N,
223 );
224
225 HIO : sn_humanio
226 generic map (
227 SWIDTH => 16,
228 BWIDTH => 5,
229 LWIDTH => 16,
230 DCWIDTH => 3)
231 port map (
232 CLK => CLK,
233 RESET => '0',
234 CE_MSEC => CE_MSEC,
235 SWI => SWI,
236 BTN => BTN,
237 LED => LED,
238 DSP_DAT => DSP_DAT,
239 DSP_DP => DSP_DP,
240 I_SWI => I_SWI,
241 I_BTN => I_BTN,
242 O_LED => O_LED,
243 O_ANO_N => O_ANO_N,
245 );
246
247 RLINK : rlink_sp2c
248 generic map (
249 BTOWIDTH => 6, -- 64 cycles access timeout
250 RTAWIDTH => 12,
251 SYSID => sysid_proj & sysid_board & sysid_vers ,
252 IFAWIDTH => 5, -- 32 word input fifo
253 OFAWIDTH => 5, -- 32 word output fifo
254 ENAPIN_RLMON => sbcntl_sbf_rlmon,
255 ENAPIN_RBMON => sbcntl_sbf_rbmon,
256 CDWIDTH => 12,
257 CDINIT => sys_conf_ser2rri_cdinit,
258 RBMON_AWIDTH => 0,
259 RBMON_RBADDR => x"ffe8")
260 port map (
261 CLK => CLK,
262 CE_USEC => CE_USEC,
263 CE_MSEC => CE_MSEC,
264 CE_INT => CE_MSEC,
265 RESET => GBL_RESET,
266 CLKS => CLKS,
268 ENAXON => SWI(1),
269 ESCFILL => '0',
270 RXSD => RXD,
271 TXSD => TXD,
272 CTS_N => CTS_N,
273 RTS_N => RTS_N,
274 RB_MREQ => RB_MREQ,
275 RB_SRES => RB_SRES,
276 RB_LAM => RB_LAM,
277 RB_STAT => RB_STAT,
278 RL_MONI => open,
280 );
281
282 TST : entity work.tst_sram
283 generic map (
284 RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
285 AWIDTH => 18)
286 port map (
287 CLK => CLK,
288 RESET => GBL_RESET,
289 RB_MREQ => RB_MREQ,
291 RB_STAT => RB_STAT,
293 SWI => SWI(7 downto 0),
294 BTN => BTN(3 downto 0),
295 LED => LED(7 downto 0),
296 DSP_DAT => DSP_DAT(15 downto 0),
298 MEM_REQ => MEM_REQ,
299 MEM_WE => MEM_WE,
305 MEM_ADDR => MEM_ADDR(17 downto 0), -- ?? FIXME ?? allow AWIDTH=20
306 MEM_BE => MEM_BE,
307 MEM_DI => MEM_DI,
308 MEM_DO => MEM_DO
309 );
310
311 MEM_ADDR(19 downto 18) <= (others=>'0'); --?? FIXME ?? allow AWIDTH=20
312
314
315 MEMCTL: sramif_mig_nexys4d -- SRAM to MIG iface -----------------
316 port map (
317 CLK => CLK,
318 RESET => MEM_RESET,
319 REQ => MEM_REQ,
320 WE => MEM_WE,
321 BUSY => MEM_BUSY,
322 ACK_R => MEM_ACK_R,
323 ACK_W => MEM_ACK_W,
324 ACT_R => MEM_ACT_R,
325 ACT_W => MEM_ACT_W,
326 ADDR => MEM_ADDR,
327 BE => MEM_BE,
328 DI => MEM_DI,
329 DO => MEM_DO,
330 CLKMIG => CLK100_BUF,
331 CLKREF => CLKREF,
332 TEMP => XADC_TEMP,
333 MONI => MIG_MONI,
334 DDR2_DQ => DDR2_DQ,
335 DDR2_DQS_P => DDR2_DQS_P,
336 DDR2_DQS_N => DDR2_DQS_N,
337 DDR2_ADDR => DDR2_ADDR,
338 DDR2_BA => DDR2_BA,
339 DDR2_RAS_N => DDR2_RAS_N,
340 DDR2_CAS_N => DDR2_CAS_N,
341 DDR2_WE_N => DDR2_WE_N,
342 DDR2_CK_P => DDR2_CK_P,
343 DDR2_CK_N => DDR2_CK_N,
344 DDR2_CKE => DDR2_CKE,
345 DDR2_CS_N => DDR2_CS_N,
346 DDR2_DM => DDR2_DM,
347 DDR2_ODT => DDR2_ODT
348 );
349
350 SMRB : sysmonx_rbus_base
351 generic map ( -- use default INIT_ (Vccint=1.00)
352 CLK_MHZ => sys_conf_clksys_mhz,
354 port map (
355 CLK => CLK,
356 RESET => GBL_RESET,
357 RB_MREQ => RB_MREQ,
359 ALM => open,
360 OT => open,
361 TEMP => XADC_TEMP
362 );
363
364 UARB : rbd_usracc
365 port map (
366 CLK => CLK,
367 RB_MREQ => RB_MREQ,
369 );
370
371 RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
372 port map (
373 RB_SRES_1 => RB_SRES_TST,
374 RB_SRES_2 => RB_SRES_SYSMON,
375 RB_SRES_3 => RB_SRES_USRACC,
376 RB_SRES_OR => RB_SRES
377 );
378
379 RB_LAM(0) <= RB_LAM_TST;
380
381 DSP_DP(3) <= not SER_MONI.txok;
382 DSP_DP(2) <= SER_MONI.txact;
383 DSP_DP(1) <= not SER_MONI.rxok;
384 DSP_DP(0) <= SER_MONI.rxact;
385
386 DSP_DP(7 downto 4) <= "0010";
387 DSP_DAT(31 downto 16) <= SER_MONI.abclkdiv(11 downto 0) &
388 '0' & SER_MONI.abclkdiv_f;
389
390 -- setup unused outputs in nexys4
391 O_RGBLED0 <= (others=>'0');
392 O_RGBLED1 <= (others=>not I_BTNRST_N);
393
394end syn;
395
in I std_ulogic
Definition: bufg_unisim.vhd:29
out O std_ulogic
Definition: bufg_unisim.vhd:27
in CLK slbit
Definition: rbd_usracc.vhd:40
in RB_MREQ rb_mreq_type
Definition: rbd_usracc.vhd:41
out RB_SRES rb_sres_type
Definition: rbd_usracc.vhd:43
Definition: rblib.vhd:32
std_logic_vector( 19 downto 0) slv20
Definition: slvtypes.vhd:53
std_logic_vector( 12 downto 0) slv13
Definition: slvtypes.vhd:45
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 11 downto 0) slv12
Definition: slvtypes.vhd:44
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 0 downto 0) slv1
Definition: slvtypes.vhd:33
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:63
out O_LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:66
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:62
DCWIDTH positive := 2
Definition: sn_humanio.vhd:53
out SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:59
in I_BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:65
LWIDTH positive := 8
Definition: sn_humanio.vhd:52
in I_SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:64
out O_SEG_N slv8
Definition: sn_humanio.vhd:69
SWIDTH positive := 8
Definition: sn_humanio.vhd:50
out BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:60
in CLK slbit
Definition: sn_humanio.vhd:56
BWIDTH positive := 4
Definition: sn_humanio.vhd:51
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:67
in LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:61
in RESET slbit := '0'
Definition: sn_humanio.vhd:57
in CE_MSEC slbit
Definition: sn_humanio.vhd:58
slv12 :=( others => '0') XADC_TEMP
slv32 :=( others => '0') DSP_DAT
slv16 :=( others => '0') SWI
slv4 :=( others => '0') RB_STAT
sramif2migui_moni_type := sramif2migui_moni_init MIG_MONI
slv32 :=( others => '0') MEM_DI
rb_sres_type := rb_sres_init RB_SRES_SYSMON
rb_mreq_type := rb_mreq_init RB_MREQ
serport_moni_type := serport_moni_init SER_MONI
slv32 :=( others => '0') MEM_DO
rb_sres_type := rb_sres_init RB_SRES
slv16 :=( others => '0') LED
rb_sres_type := rb_sres_init RB_SRES_TST
slv8 :=( others => '0') DSP_DP
slv16 := x"fb00" rbaddr_sysmon
rb_sres_type := rb_sres_init RB_SRES_USRACC
slv16 :=( others => '0') RB_LAM
slv4 :=( others => '0') MEM_BE
slv5 :=( others => '0') BTN
slv16 := x"0104" sysid_proj
slv20 :=( others => '0') MEM_ADDR
inout DDR2_DQS_P slv2
inout DDR2_DQS_N slv2
inout DDR2_DQ slv16
CLK_MHZ integer := 250
RB_ADDR slv16 := x"fb00"
in RB_MREQ rb_mreq_type
out RB_SRES rb_sres_type
in RESET slbit := '0'
in MEM_BUSY slbit
Definition: tst_sram.vhd:182
out MEM_DI slv32
Definition: tst_sram.vhd:189
AWIDTH natural := 18
Definition: tst_sram.vhd:167
in RESET slbit
Definition: tst_sram.vhd:170
in MEM_ACK_W slbit
Definition: tst_sram.vhd:184
out MEM_RESET slbit
Definition: tst_sram.vhd:179
out RB_LAM slbit
Definition: tst_sram.vhd:174
in BTN slv4
Definition: tst_sram.vhd:176
out MEM_BE slv4
Definition: tst_sram.vhd:188
out RB_STAT slv4
Definition: tst_sram.vhd:173
in MEM_ACT_W slbit
Definition: tst_sram.vhd:186
in CLK slbit
Definition: tst_sram.vhd:169
RB_ADDR slv16 := slv( to_unsigned( 2#0000000000000000#, 16) )
Definition: tst_sram.vhd:166
out MEM_REQ slbit
Definition: tst_sram.vhd:180
in RB_MREQ rb_mreq_type
Definition: tst_sram.vhd:171
out MEM_ADDR slv( AWIDTH- 1 downto 0)
Definition: tst_sram.vhd:187
in MEM_ACT_R slbit
Definition: tst_sram.vhd:185
in MEM_ACK_R slbit
Definition: tst_sram.vhd:183
out RB_SRES rb_sres_type
Definition: tst_sram.vhd:172
in MEM_DO slv32
Definition: tst_sram.vhd:191
out MEM_WE slbit
Definition: tst_sram.vhd:181
out DSP_DAT slv16
Definition: tst_sram.vhd:178
out LED slv8
Definition: tst_sram.vhd:177
in SWI slv8
Definition: tst_sram.vhd:175
Definition: xlib.vhd:35