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W11 CPU core and support modules
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sys_tst_rlink_b3.vhd
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1-- $Id: sys_tst_rlink_b3.vhd 1247 2022-07-06 07:04:33Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_tst_rlink_b3 - syn
7-- Description: rlink tester design for basys3
8--
9-- Dependencies: vlib/xlib/s7_cmt_sfs
10-- vlib/genlib/clkdivce
11-- bplib/bpgen/bp_rs232_2line_iob
12-- bplib/bpgen/sn_humanio_rbus
13-- vlib/rlink/rlink_sp1c
14-- rbd_tst_rlink
15-- bplib/sysmon/sysmonx_rbus_base
16-- vlib/rbus/rbd_usracc
17-- vlib/rbus/rb_sres_or_4
18--
19-- Test bench: tb/tb_tst_rlink_b3
20--
21-- Target Devices: generic
22-- Tool versions: viv 2014.4-2022.1; ghdl 0.31-2.0.0
23--
24-- Synthesized (viv):
25-- Date Rev viv Target flop lutl lutm bram slic
26-- 2022-07-05 1247 2022.1 xc7a35t-1 1039 1492 34 3.0 527
27-- 2019-02-02 1108 2018.3 xc7a35t-1 1040 1594 36 3.0 546
28-- 2019-02-02 1108 2017.2 xc7a35t-1 1040 1682 36 3.0 587
29-- 2016-03-27 753 2015.4 xc7a35t-1 986 1352 36 3.0 473 meminf
30-- 2016-03-13 743 2015.4 xc7a35t-1 988 1372 64 4.5 503 +XADC
31-- 2015-01-30 636 2014.4 xc7a35t-1 946 1319 64 4.5 476
32--
33-- Revision History:
34-- Date Rev Version Comment
35-- 2016-04-02 758 1.1.3 add rbd_usracc (bitfile+jtag timestamp access)
36-- 2016-03-19 748 1.1.2 define rlink SYSID
37-- 2016-03-18 745 1.1.1 hardwire XON=1
38-- 2016-03-12 741 1.1 add sysmon_rbus
39-- 2016-02-26 735 1.0.2 use s7_cmt_sfs
40-- 2015-04-11 666 1.0.1 rearrange XON handling
41-- 2015-01-16 636 1.0 Initial version (derived from sys_tst_rlink_n3)
42------------------------------------------------------------------------------
43-- Usage of Basys 3 Switches, Buttons, LEDs:
44--
45-- SWI(7:2): no function (only connected to sn_humanio_rbus)
46-- SWI(1): -unused-
47-- SWI(0): -unused-
48--
49-- LED(7): SER_MONI.abact
50-- LED(6:2): no function (only connected to sn_humanio_rbus)
51-- LED(1): timer 1 busy
52-- LED(0): timer 0 busy
53--
54-- DSP: SER_MONI.clkdiv (from auto bauder)
55-- DP(3): not SER_MONI.txok (shows tx back pressure)
56-- DP(2): SER_MONI.txact (shows tx activity)
57-- DP(1): not SER_MONI.rxok (shows rx back pressure)
58-- DP(0): SER_MONI.rxact (shows rx activity)
59--
60
61library ieee;
62use ieee.std_logic_1164.all;
63
64use work.slvtypes.all;
65use work.xlib.all;
66use work.genlib.all;
67use work.serportlib.all;
68use work.rblib.all;
69use work.rbdlib.all;
70use work.rlinklib.all;
71use work.bpgenlib.all;
72use work.bpgenrbuslib.all;
73use work.sysmonrbuslib.all;
74use work.sys_conf.all;
75
76-- ----------------------------------------------------------------------------
77
78entity sys_tst_rlink_b3 is -- top level
79 -- implements basys3_aif
80 port (
81 I_CLK100 : in slbit; -- 100 MHz clock
82 I_RXD : in slbit; -- receive data (board view)
83 O_TXD : out slbit; -- transmit data (board view)
84 I_SWI : in slv16; -- b3 switches
85 I_BTN : in slv5; -- b3 buttons
86 O_LED : out slv16; -- b3 leds
87 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
88 O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
89 );
91
92architecture syn of sys_tst_rlink_b3 is
93
94 signal CLK : slbit := '0';
95
96 signal RXD : slbit := '1';
97 signal TXD : slbit := '0';
98
99 signal SWI : slv16 := (others=>'0');
100 signal BTN : slv5 := (others=>'0');
101 signal LED : slv16 := (others=>'0');
102 signal DSP_DAT : slv16 := (others=>'0');
103 signal DSP_DP : slv4 := (others=>'0');
104
105 signal RESET : slbit := '0';
106 signal CE_USEC : slbit := '0';
107 signal CE_MSEC : slbit := '0';
108
109 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
110 signal RB_SRES : rb_sres_type := rb_sres_init;
111 signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
112 signal RB_SRES_TST : rb_sres_type := rb_sres_init;
113 signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
114 signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
115
116 signal RB_LAM : slv16 := (others=>'0');
117 signal RB_STAT : slv4 := (others=>'0');
118
119 signal SER_MONI : serport_moni_type := serport_moni_init;
120 signal STAT : slv8 := (others=>'0');
121
122 constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
123 constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
124
125 constant sysid_proj : slv16 := x"0101"; -- tst_rlink
126 constant sysid_board : slv8 := x"06"; -- basys3
127 constant sysid_vers : slv8 := x"00";
128
129begin
130
131 assert (sys_conf_clksys mod 1000000) = 0
132 report "assert sys_conf_clksys on MHz grid"
133 severity failure;
134
135 RESET <= '0'; -- so far not used
136
137 GEN_CLKSYS : s7_cmt_sfs
138 generic map (
139 VCO_DIVIDE => sys_conf_clksys_vcodivide,
140 VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
141 OUT_DIVIDE => sys_conf_clksys_outdivide,
142 CLKIN_PERIOD => 10.0,
143 CLKIN_JITTER => 0.01,
144 STARTUP_WAIT => false,
145 GEN_TYPE => sys_conf_clksys_gentype)
146 port map (
147 CLKIN => I_CLK100,
148 CLKFX => CLK,
149 LOCKED => open
150 );
151
152 CLKDIV : clkdivce
153 generic map (
154 CDUWIDTH => 7,
155 USECDIV => sys_conf_clksys_mhz,
156 MSECDIV => 1000)
157 port map (
158 CLK => CLK,
159 CE_USEC => CE_USEC,
161 );
162
163 IOB_RS232 : bp_rs232_2line_iob
164 port map (
165 CLK => CLK,
166 RXD => RXD,
167 TXD => TXD,
168 I_RXD => I_RXD,
169 O_TXD => O_TXD
170 );
171
172 HIO : sn_humanio_rbus
173 generic map (
174 SWIDTH => 16,
175 BWIDTH => 5,
176 LWIDTH => 16,
177 DEBOUNCE => sys_conf_hio_debounce,
179 port map (
180 CLK => CLK,
181 RESET => RESET,
182 CE_MSEC => CE_MSEC,
183 RB_MREQ => RB_MREQ,
185 SWI => SWI,
186 BTN => BTN,
187 LED => LED,
188 DSP_DAT => DSP_DAT,
189 DSP_DP => DSP_DP,
190 I_SWI => I_SWI,
191 I_BTN => I_BTN,
192 O_LED => O_LED,
193 O_ANO_N => O_ANO_N,
195 );
196
197 RLINK : rlink_sp1c
198 generic map (
199 BTOWIDTH => 6,
200 RTAWIDTH => 12,
201 SYSID => sysid_proj & sysid_board & sysid_vers ,
202 IFAWIDTH => 5,
203 OFAWIDTH => 5,
204 ENAPIN_RLMON => sbcntl_sbf_rlmon,
205 ENAPIN_RBMON => sbcntl_sbf_rbmon,
206 CDWIDTH => 12,
207 CDINIT => sys_conf_ser2rri_cdinit,
208 RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink
209 RBMON_RBADDR => (others=>'0'))
210 port map (
211 CLK => CLK,
212 CE_USEC => CE_USEC,
213 CE_MSEC => CE_MSEC,
214 CE_INT => CE_MSEC,
215 RESET => RESET,
216 ENAXON => '1',
217 ESCFILL => '0',
218 RXSD => RXD,
219 TXSD => TXD,
220 CTS_N => '0',
221 RTS_N => open,
222 RB_MREQ => RB_MREQ,
223 RB_SRES => RB_SRES,
224 RB_LAM => RB_LAM,
225 RB_STAT => RB_STAT,
226 RL_MONI => open,
228 );
229
230 RBDTST : entity work.rbd_tst_rlink
231 port map (
232 CLK => CLK,
233 RESET => RESET,
234 CE_USEC => CE_USEC,
235 RB_MREQ => RB_MREQ,
237 RB_LAM => RB_LAM,
238 RB_STAT => RB_STAT,
240 RXSD => RXD,
241 RXACT => SER_MONI.rxact,
242 STAT => STAT
243 );
244
245 SMRB : if sys_conf_rbd_sysmon generate
247 generic map ( -- use default INIT_ (Vccint=1.00)
248 CLK_MHZ => sys_conf_clksys_mhz,
250 port map (
251 CLK => CLK,
252 RESET => RESET,
253 RB_MREQ => RB_MREQ,
255 ALM => open,
256 OT => open,
257 TEMP => open
258 );
259 end generate SMRB;
260
261 UARB : rbd_usracc
262 port map (
263 CLK => CLK,
264 RB_MREQ => RB_MREQ,
266 );
267
268 RB_SRES_OR1 : rb_sres_or_4
269 port map (
275 );
276
277 DSP_DAT <= SER_MONI.abclkdiv;
278
279 DSP_DP(3) <= not SER_MONI.txok;
280 DSP_DP(2) <= SER_MONI.txact;
281 DSP_DP(1) <= not SER_MONI.rxok;
282 DSP_DP(0) <= SER_MONI.rxact;
283
284 LED(15 downto 8) <= SWI(15 downto 8);
285 LED(7) <= SER_MONI.abact;
286 LED(6 downto 2) <= (others=>'0');
287 LED(1) <= STAT(1);
288 LED(0) <= STAT(0);
289
290end syn;
out CE_MSEC slbit
Definition: clkdivce.vhd:39
USECDIV positive := 50
Definition: clkdivce.vhd:33
CDUWIDTH positive := 6
Definition: clkdivce.vhd:32
out CE_USEC slbit
Definition: clkdivce.vhd:37
MSECDIV positive := 1000
Definition: clkdivce.vhd:34
in CLK slbit
Definition: clkdivce.vhd:36
in RB_SRES_2 rb_sres_type := rb_sres_init
in RB_SRES_3 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
in RB_SRES_4 rb_sres_type := rb_sres_init
in CLK slbit
Definition: rbd_usracc.vhd:40
in RB_MREQ rb_mreq_type
Definition: rbd_usracc.vhd:41
out RB_SRES rb_sres_type
Definition: rbd_usracc.vhd:43
Definition: rblib.vhd:32
VCO_DIVIDE positive := 1
GEN_TYPE string := "PLL"
CLKIN_PERIOD real := 10.0
OUT_DIVIDE positive := 1
in CLKIN slbit
CLKIN_JITTER real := 0.01
STARTUP_WAIT boolean := false
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
DEBOUNCE boolean := true
out O_LED slv( LWIDTH- 1 downto 0)
RB_ADDR slv16 := x"fef0"
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
out SWI slv( SWIDTH- 1 downto 0)
in I_BTN slv( BWIDTH- 1 downto 0)
LWIDTH positive := 8
in I_SWI slv( SWIDTH- 1 downto 0)
SWIDTH positive := 8
out BTN slv( BWIDTH- 1 downto 0)
in RB_MREQ rb_mreq_type
BWIDTH positive := 4
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
out RB_SRES rb_sres_type
in LED slv( LWIDTH- 1 downto 0)
in RESET slbit := '0'
CLK_MHZ integer := 250
RB_ADDR slv16 := x"fb00"
in RB_MREQ rb_mreq_type
out RB_SRES rb_sres_type
in RESET slbit := '0'
Definition: xlib.vhd:35