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W11 CPU core and support modules
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sys_tst_sram_arty.vhd
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1-- $Id: sys_tst_sram_arty.vhd 1247 2022-07-06 07:04:33Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2018-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_tst_sram_arty - syn
7-- Description: test of arty ddr and its mig controller
8--
9-- Dependencies: vlib/xlib/bufg_unisim
10-- bplib/bpgen/s7_cmt_1ce1ce2c
11-- cdclib/cdc_signal_s1_as
12-- bplib/bpgen/bp_rs232_2line_iob
13-- rlink/rlink_sp2c
14-- tst_sram
15-- bplib/arty/sramif_mig_arty
16-- bplib/bpgen/sn_humanio_eum_rbus
17-- bplib/sysmon/sysmonx_rbus_arty
18-- rbus/rbd_usracc
19-- rbus/rb_sres_or_4
20--
21-- Test bench: tb/tb_tst_sram_arty
22--
23-- Target Devices: generic
24-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0
25--
26-- Synthesized (viv):
27-- Date Rev viv Target flop lutl lutm bram slic
28-- 2022-07-05 1247 2022.1 xc7a35t-1l 4648 4594 611 5 1849
29-- 2019-02-02 1108 2018.3 xc7a35t-1l 4648 4968 644 5 1983
30-- 2019-02-02 1108 2017.2 xc7a35t-1l 4643 5334 644 5 1929
31-- 2019-01-02 1101 2017.2 xc7a35t-1l 4643 5334 644 5 1929
32--
33-- Revision History:
34-- Date Rev Version Comment
35-- 2022-07-05 1247 1.0.1 use bufg_unisim
36-- 2018-12-20 1090 1.0 Initial version
37-- 2018-11-17 1071 0.1 First draft (derived from sys_tst_sram_c7)
38------------------------------------------------------------------------------
39
40library ieee;
41use ieee.std_logic_1164.all;
42use ieee.numeric_std.all;
43
44use work.slvtypes.all;
45use work.xlib.all;
46use work.cdclib.all;
47use work.serportlib.all;
48use work.rblib.all;
49use work.rbdlib.all;
50use work.rlinklib.all;
51use work.bpgenlib.all;
52use work.bpgenrbuslib.all;
53use work.sysmonrbuslib.all;
54use work.miglib.all;
55use work.miglib_arty.all;
56use work.sys_conf.all;
57
58-- ----------------------------------------------------------------------------
59
60entity sys_tst_sram_arty is -- top level
61 -- implements arty_sram_aif
62 port (
63 I_CLK100 : in slbit; -- 100 MHz clock
64 I_RXD : in slbit; -- receive data (board view)
65 O_TXD : out slbit; -- transmit data (board view)
66 I_SWI : in slv4; -- arty switches
67 I_BTN : in slv4; -- arty buttons
68 O_LED : out slv4; -- arty leds
69 O_RGBLED0 : out slv3; -- arty rgb-led 0
70 O_RGBLED1 : out slv3; -- arty rgb-led 1
71 O_RGBLED2 : out slv3; -- arty rgb-led 2
72 O_RGBLED3 : out slv3; -- arty rgb-led 3
73 A_VPWRN : in slv4; -- arty pwrmon (neg)
74 A_VPWRP : in slv4; -- arty pwrmon (pos)
75 DDR3_DQ : inout slv16; -- dram: data in/out
76 DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
77 DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
78 DDR3_ADDR : out slv14; -- dram: address
79 DDR3_BA : out slv3; -- dram: bank address
80 DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
81 DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
82 DDR3_WE_N : out slbit; -- dram: write enable (act.low)
83 DDR3_RESET_N : out slbit; -- dram: reset (act.low)
84 DDR3_CK_P : out slv1; -- dram: clock (diff-p)
85 DDR3_CK_N : out slv1; -- dram: clock (diff-n)
86 DDR3_CKE : out slv1; -- dram: clock enable
87 DDR3_CS_N : out slv1; -- dram: chip select (act.low)
88 DDR3_DM : out slv2; -- dram: data input mask
89 DDR3_ODT : out slv1 -- dram: on-die termination
90 );
92
93architecture syn of sys_tst_sram_arty is
94
95 signal CLK100_BUF : slbit := '0';
96
97 signal CLK : slbit := '0';
98
99 signal CE_USEC : slbit := '0';
100 signal CE_MSEC : slbit := '0';
101
102 signal CLKS : slbit := '0';
103 signal CES_MSEC : slbit := '0';
104
105 signal CLKMIG : slbit := '0';
106 signal CLKREF : slbit := '0';
107
108 signal LOCKED : slbit := '0'; -- raw LOCKED
109 signal LOCKED_CLK : slbit := '0'; -- sync'ed to CLK
110
111 signal GBL_RESET : slbit := '0';
112 signal MEM_RESET : slbit := '0';
113 signal MEM_RESET_RRI : slbit := '0';
114
115 signal RXD : slbit := '1';
116 signal TXD : slbit := '0';
117
118 signal SWI : slv16 := (others=>'0');
119 signal BTN : slv5 := (others=>'0');
120 signal LED : slv16 := (others=>'0');
121 signal DSP_DAT : slv32 := (others=>'0');
122 signal DSP_DP : slv8 := (others=>'0');
123
124 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
125 signal RB_SRES : rb_sres_type := rb_sres_init;
126 signal RB_LAM : slv16 := (others=>'0');
127 signal RB_STAT : slv4 := (others=>'0');
128
129 signal SER_MONI : serport_moni_type := serport_moni_init;
130
131 signal RB_SRES_TST : rb_sres_type := rb_sres_init;
132 signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
133 signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
134 signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
135
136 signal RB_LAM_TST : slbit := '0';
137
138 signal MEM_REQ : slbit := '0';
139 signal MEM_WE : slbit := '0';
140 signal MEM_BUSY : slbit := '0';
141 signal MEM_ACK_R : slbit := '0';
142 signal MEM_ACK_W : slbit := '0';
143 signal MEM_ACT_R : slbit := '0';
144 signal MEM_ACT_W : slbit := '0';
145 signal MEM_ADDR : slv20 := (others=>'0');
146 signal MEM_BE : slv4 := (others=>'0');
147 signal MEM_DI : slv32 := (others=>'0');
148 signal MEM_DO : slv32 := (others=>'0');
149
150 signal MIG_MONI : sramif2migui_moni_type := sramif2migui_moni_init;
151 signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
152
153 signal R_DIMCNT : slv2 := (others=>'0');
154 signal R_DIMFLG : slbit := '0';
155
156 constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
157 constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
158
159 constant sysid_proj : slv16 := x"0104"; -- tst_sram
160 constant sysid_board : slv8 := x"07"; -- arty
161 constant sysid_vers : slv8 := x"00";
162
163begin
164
165 CLK100_BUFG: bufg_unisim
166 port map (
167 I => I_CLK100,
168 O => CLK100_BUF
169 );
170
171 GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
172 generic map (
173 CLKIN_PERIOD => 10.0,
174 CLKIN_JITTER => 0.01,
175 STARTUP_WAIT => false,
176 CLK0_VCODIV => sys_conf_clksys_vcodivide,
177 CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
178 CLK0_OUTDIV => sys_conf_clksys_outdivide,
179 CLK0_GENTYPE => sys_conf_clksys_gentype,
180 CLK0_CDUWIDTH => 7,
181 CLK0_USECDIV => sys_conf_clksys_mhz,
182 CLK0_MSECDIV => 1000,
183 CLK1_VCODIV => sys_conf_clkser_vcodivide,
184 CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
185 CLK1_OUTDIV => sys_conf_clkser_outdivide,
186 CLK1_GENTYPE => sys_conf_clkser_gentype,
187 CLK1_CDUWIDTH => 7,
188 CLK1_USECDIV => sys_conf_clkser_mhz,
189 CLK1_MSECDIV => 1000,
190 CLK23_VCODIV => 1,
191 CLK23_VCOMUL => 10, -- vco 1000 MHz
192 CLK2_OUTDIV => 6, -- mig sys 166.6 MHz
193 CLK3_OUTDIV => 5, -- mig ref 200.0 MHz
194 CLK23_GENTYPE => "PLL")
195 port map (
196 CLKIN => CLK100_BUF,
197 CLK0 => CLK,
198 CE0_USEC => CE_USEC,
199 CE0_MSEC => CE_MSEC,
200 CLK1 => CLKS,
201 CE1_USEC => open,
202 CE1_MSEC => CES_MSEC,
203 CLK2 => CLKMIG,
204 CLK3 => CLKREF,
205 LOCKED => LOCKED
206 );
207
208 CDC_CLK_LOCKED : cdc_signal_s1_as
209 port map (
210 CLKO => CLK,
211 DI => LOCKED,
212 DO => LOCKED_CLK
213 );
214
215 GBL_RESET <= not LOCKED_CLK;
216
217 IOB_RS232 : bp_rs232_2line_iob
218 port map (
219 CLK => CLKS,
220 RXD => RXD,
221 TXD => TXD,
222 I_RXD => I_RXD,
223 O_TXD => O_TXD
224 );
225
226 RLINK : rlink_sp2c
227 generic map (
228 BTOWIDTH => 8, -- 256 cycles, for slow mem iface
229 RTAWIDTH => 12,
230 SYSID => sysid_proj & sysid_board & sysid_vers ,
231 IFAWIDTH => 5, -- 32 word input fifo
232 OFAWIDTH => 5, -- 32 word output fifo
233 ENAPIN_RLMON => sbcntl_sbf_rlmon,
234 ENAPIN_RBMON => sbcntl_sbf_rbmon,
235 CDWIDTH => 12,
236 CDINIT => sys_conf_ser2rri_cdinit,
237 RBMON_AWIDTH => 0,
239 port map (
240 CLK => CLK,
241 CE_USEC => CE_USEC,
242 CE_MSEC => CE_MSEC,
243 CE_INT => CE_MSEC,
244 RESET => GBL_RESET,
245 CLKS => CLKS,
247 ENAXON => '1',
248 ESCFILL => '0',
249 RXSD => RXD,
250 TXSD => TXD,
251 CTS_N => '0',
252 RTS_N => open,
253 RB_MREQ => RB_MREQ,
254 RB_SRES => RB_SRES,
255 RB_LAM => RB_LAM,
256 RB_STAT => RB_STAT,
257 RL_MONI => open,
259 );
260
261 TST : entity work.tst_sram
262 generic map (
263 RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
264 AWIDTH => 18)
265 port map (
266 CLK => CLK,
267 RESET => GBL_RESET,
268 RB_MREQ => RB_MREQ,
270 RB_STAT => RB_STAT,
272 SWI => SWI(7 downto 0),
273 BTN => BTN(3 downto 0),
274 LED => LED(7 downto 0),
275 DSP_DAT => DSP_DAT(15 downto 0),
277 MEM_REQ => MEM_REQ,
278 MEM_WE => MEM_WE,
284 MEM_ADDR => MEM_ADDR(17 downto 0), -- ?? FIXME ?? allow AWIDTH=20
285 MEM_BE => MEM_BE,
286 MEM_DI => MEM_DI,
287 MEM_DO => MEM_DO
288 );
289
290 MEM_ADDR(19 downto 18) <= (others=>'0'); --?? FIXME ?? allow AWIDTH=20
291
293
294 MEMCTL: sramif_mig_arty -- SRAM to MIG iface -----------------
295 port map (
296 CLK => CLK,
297 RESET => MEM_RESET,
298 REQ => MEM_REQ,
299 WE => MEM_WE,
300 BUSY => MEM_BUSY,
301 ACK_R => MEM_ACK_R,
302 ACK_W => MEM_ACK_W,
303 ACT_R => MEM_ACT_R,
304 ACT_W => MEM_ACT_W,
305 ADDR => MEM_ADDR,
306 BE => MEM_BE,
307 DI => MEM_DI,
308 DO => MEM_DO,
309 CLKMIG => CLKMIG,
310 CLKREF => CLKREF,
311 TEMP => XADC_TEMP,
312 MONI => MIG_MONI,
313 DDR3_DQ => DDR3_DQ,
314 DDR3_DQS_P => DDR3_DQS_P,
315 DDR3_DQS_N => DDR3_DQS_N,
316 DDR3_ADDR => DDR3_ADDR,
317 DDR3_BA => DDR3_BA,
318 DDR3_RAS_N => DDR3_RAS_N,
319 DDR3_CAS_N => DDR3_CAS_N,
320 DDR3_WE_N => DDR3_WE_N,
321 DDR3_RESET_N => DDR3_RESET_N,
322 DDR3_CK_P => DDR3_CK_P,
323 DDR3_CK_N => DDR3_CK_N,
324 DDR3_CKE => DDR3_CKE,
325 DDR3_CS_N => DDR3_CS_N,
326 DDR3_DM => DDR3_DM,
327 DDR3_ODT => DDR3_ODT
328 );
329
331 generic map (
332 SWIDTH => 16,
333 BWIDTH => 5,
334 LWIDTH => 16,
335 DCWIDTH => 3)
336 port map (
337 CLK => CLK,
338 RESET => '0',
339 RB_MREQ => RB_MREQ,
341 SWI => SWI,
342 BTN => BTN,
343 LED => LED,
344 DSP_DAT => DSP_DAT,
345 DSP_DP => DSP_DP
346 );
347
349 generic map ( -- use default INIT_ (LP: Vccint=0.95)
350 CLK_MHZ => sys_conf_clksys_mhz,
352 port map (
353 CLK => CLK,
354 RESET => GBL_RESET,
355 RB_MREQ => RB_MREQ,
357 ALM => open,
358 OT => open,
359 TEMP => XADC_TEMP,
360 VPWRN => A_VPWRN,
361 VPWRP => A_VPWRP
362 );
363
364 UARB : rbd_usracc
365 port map (
366 CLK => CLK,
367 RB_MREQ => RB_MREQ,
369 );
370
371 RB_SRES_OR : rb_sres_or_4 -- rbus or ---------------------------
372 port map (
373 RB_SRES_1 => RB_SRES_TST,
374 RB_SRES_2 => RB_SRES_HIO,
375 RB_SRES_3 => RB_SRES_SYSMON,
376 RB_SRES_4 => RB_SRES_USRACC,
377 RB_SRES_OR => RB_SRES
378 );
379
380 proc_dim: process (CLKMIG)
381 begin
382
383 if rising_edge(CLKMIG) then
384 R_DIMCNT <= slv(unsigned(R_DIMCNT) + 1);
385 if unsigned(R_DIMCNT) = 0 then
386 R_DIMFLG <= '1';
387 else
388 R_DIMFLG <= '0';
389 end if;
390 end if;
391
392 end process proc_dim;
393
394 RB_LAM(0) <= RB_LAM_TST;
395
396 O_LED(1) <= SER_MONI.txact;
397 O_LED(0) <= SER_MONI.rxact;
398
399 DSP_DP(3) <= not SER_MONI.txok;
400 DSP_DP(2) <= SER_MONI.txact;
401 DSP_DP(1) <= not SER_MONI.rxok;
402 DSP_DP(0) <= SER_MONI.rxact;
403
404 DSP_DP(7 downto 4) <= "0010";
405 DSP_DAT(31 downto 16) <= SER_MONI.abclkdiv(11 downto 0) &
406 '0' & SER_MONI.abclkdiv_f;
407
408 -- red LED for serious error conditions
409 O_RGBLED0(0) <= R_DIMFLG and (I_BTN(0) or not LOCKED);
410 O_RGBLED1(0) <= R_DIMFLG and (I_BTN(0));
411 O_RGBLED2(0) <= R_DIMFLG and (I_BTN(0) or MIG_MONI.miguirst);
412 O_RGBLED3(0) <= R_DIMFLG and (I_BTN(0) or MIG_MONI.migcacow);
413
414 -- green LED for activity
415 O_RGBLED0(1) <= R_DIMFLG and (I_BTN(1) or MEM_ACT_R);
416 O_RGBLED1(1) <= R_DIMFLG and (I_BTN(1) or MEM_ACT_W);
417 O_RGBLED2(1) <= R_DIMFLG and (I_BTN(1) or (MIG_MONI.migcbusy xor I_BTN(3)));
418 O_RGBLED3(1) <= R_DIMFLG and (I_BTN(1) or MIG_MONI.migwbusy);
419
420 -- blue LED currently unused
421 O_RGBLED0(2) <= R_DIMFLG and (I_BTN(2));
422 O_RGBLED1(2) <= R_DIMFLG and (I_BTN(2));
423 O_RGBLED2(2) <= R_DIMFLG and (I_BTN(2));
424 O_RGBLED3(2) <= R_DIMFLG and (I_BTN(2));
425
426end syn;
427
in I std_ulogic
Definition: bufg_unisim.vhd:29
out O std_ulogic
Definition: bufg_unisim.vhd:27
in CLK slbit
Definition: rbd_usracc.vhd:40
in RB_MREQ rb_mreq_type
Definition: rbd_usracc.vhd:41
out RB_SRES rb_sres_type
Definition: rbd_usracc.vhd:43
Definition: rblib.vhd:32
std_logic_vector( 13 downto 0) slv14
Definition: slvtypes.vhd:46
std_logic_vector( 19 downto 0) slv20
Definition: slvtypes.vhd:53
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 11 downto 0) slv12
Definition: slvtypes.vhd:44
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 0 downto 0) slv1
Definition: slvtypes.vhd:33
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
out SWI slv( SWIDTH- 1 downto 0)
out BTN slv( BWIDTH- 1 downto 0)
in RB_MREQ rb_mreq_type
out RB_SRES rb_sres_type
in LED slv( LWIDTH- 1 downto 0)
slv16 := x"ffe8" rbaddr_rbmon
slv12 :=( others => '0') XADC_TEMP
slv32 :=( others => '0') DSP_DAT
slv16 :=( others => '0') SWI
slv4 :=( others => '0') RB_STAT
sramif2migui_moni_type := sramif2migui_moni_init MIG_MONI
slv32 :=( others => '0') MEM_DI
rb_sres_type := rb_sres_init RB_SRES_SYSMON
rb_mreq_type := rb_mreq_init RB_MREQ
serport_moni_type := serport_moni_init SER_MONI
slv2 :=( others => '0') R_DIMCNT
slv32 :=( others => '0') MEM_DO
rb_sres_type := rb_sres_init RB_SRES
slv16 :=( others => '0') LED
rb_sres_type := rb_sres_init RB_SRES_TST
slv8 :=( others => '0') DSP_DP
slv16 := x"fb00" rbaddr_sysmon
rb_sres_type := rb_sres_init RB_SRES_USRACC
slv16 :=( others => '0') RB_LAM
rb_sres_type := rb_sres_init RB_SRES_HIO
slv4 :=( others => '0') MEM_BE
slv5 :=( others => '0') BTN
slv16 := x"0104" sysid_proj
slv20 :=( others => '0') MEM_ADDR
in VPWRP slv4 :=( others => '0')
CLK_MHZ integer := 250
RB_ADDR slv16 := x"fb00"
in RB_MREQ rb_mreq_type
out RB_SRES rb_sres_type
in VPWRN slv4 :=( others => '0')
in RESET slbit := '0'
in MEM_BUSY slbit
Definition: tst_sram.vhd:182
out MEM_DI slv32
Definition: tst_sram.vhd:189
AWIDTH natural := 18
Definition: tst_sram.vhd:167
in RESET slbit
Definition: tst_sram.vhd:170
in MEM_ACK_W slbit
Definition: tst_sram.vhd:184
out MEM_RESET slbit
Definition: tst_sram.vhd:179
out RB_LAM slbit
Definition: tst_sram.vhd:174
in BTN slv4
Definition: tst_sram.vhd:176
out MEM_BE slv4
Definition: tst_sram.vhd:188
out RB_STAT slv4
Definition: tst_sram.vhd:173
in MEM_ACT_W slbit
Definition: tst_sram.vhd:186
in CLK slbit
Definition: tst_sram.vhd:169
RB_ADDR slv16 := slv( to_unsigned( 2#0000000000000000#, 16) )
Definition: tst_sram.vhd:166
out MEM_REQ slbit
Definition: tst_sram.vhd:180
in RB_MREQ rb_mreq_type
Definition: tst_sram.vhd:171
out MEM_ADDR slv( AWIDTH- 1 downto 0)
Definition: tst_sram.vhd:187
in MEM_ACT_R slbit
Definition: tst_sram.vhd:185
in MEM_ACK_R slbit
Definition: tst_sram.vhd:183
out RB_SRES rb_sres_type
Definition: tst_sram.vhd:172
in MEM_DO slv32
Definition: tst_sram.vhd:191
out MEM_WE slbit
Definition: tst_sram.vhd:181
out DSP_DAT slv16
Definition: tst_sram.vhd:178
out LED slv8
Definition: tst_sram.vhd:177
in SWI slv8
Definition: tst_sram.vhd:175
Definition: xlib.vhd:35