41use ieee.std_logic_1164.
all;
42use ieee.numeric_std.
all;
124 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
125 signal RB_SRES : rb_sres_type := rb_sres_init;
129 signal SER_MONI : serport_moni_type := serport_moni_init;
150 signal MIG_MONI : sramif2migui_moni_type := sramif2migui_moni_init;
173 CLKIN_PERIOD =>
10.0,
174 CLKIN_JITTER =>
0.01,
175 STARTUP_WAIT => false,
176 CLK0_VCODIV => sys_conf_clksys_vcodivide,
177 CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
178 CLK0_OUTDIV => sys_conf_clksys_outdivide,
179 CLK0_GENTYPE => sys_conf_clksys_gentype,
181 CLK0_USECDIV => sys_conf_clksys_mhz,
182 CLK0_MSECDIV =>
1000,
183 CLK1_VCODIV => sys_conf_clkser_vcodivide,
184 CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
185 CLK1_OUTDIV => sys_conf_clkser_outdivide,
186 CLK1_GENTYPE => sys_conf_clkser_gentype,
188 CLK1_USECDIV => sys_conf_clkser_mhz,
189 CLK1_MSECDIV =>
1000,
194 CLK23_GENTYPE =>
"PLL")
230 SYSID => sysid_proj & sysid_board & sysid_vers ,
236 CDINIT => sys_conf_ser2rri_cdinit,
263 RB_ADDR =>
slv(to_unsigned
(2#0000000000000000#,
16)),
290 MEM_ADDR(19 downto 18) <= (others=>'0');
350 CLK_MHZ => sys_conf_clksys_mhz,
371 RB_SRES_OR :
rb_sres_or_4 -- rbus
or ---------------------------
383 if rising_edge(CLKMIG) then
392 end process proc_dim;
404 DSP_DP(7 downto 4) <= "0010";
ENAPIN_RBMON integer :=- 1
out SER_MONI serport_moni_type
ENAPIN_RLMON integer :=- 1
RBMON_RBADDR slv16 := rbaddr_rbmon
RBMON_AWIDTH natural := 0
SYSID slv32 :=( others => '0')
std_logic_vector( 13 downto 0) slv14
std_logic_vector( 19 downto 0) slv20
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 4 downto 0) slv5
std_logic_vector( 11 downto 0) slv12
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 0 downto 0) slv1
std_logic_vector( 31 downto 0) slv32
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
out SWI slv( SWIDTH- 1 downto 0)
out BTN slv( BWIDTH- 1 downto 0)
in LED slv( LWIDTH- 1 downto 0)
slv16 := x"ffe8" rbaddr_rbmon
slv12 :=( others => '0') XADC_TEMP
slv8 := x"07" sysid_board
slv32 :=( others => '0') DSP_DAT
slv16 :=( others => '0') SWI
slv4 :=( others => '0') RB_STAT
sramif2migui_moni_type := sramif2migui_moni_init MIG_MONI
slv32 :=( others => '0') MEM_DI
rb_sres_type := rb_sres_init RB_SRES_SYSMON
rb_mreq_type := rb_mreq_init RB_MREQ
serport_moni_type := serport_moni_init SER_MONI
slv2 :=( others => '0') R_DIMCNT
slv32 :=( others => '0') MEM_DO
rb_sres_type := rb_sres_init RB_SRES
slv16 :=( others => '0') LED
rb_sres_type := rb_sres_init RB_SRES_TST
slbit := '0' MEM_RESET_RRI
slv8 :=( others => '0') DSP_DP
slv16 := x"fb00" rbaddr_sysmon
rb_sres_type := rb_sres_init RB_SRES_USRACC
slv16 :=( others => '0') RB_LAM
rb_sres_type := rb_sres_init RB_SRES_HIO
slv4 :=( others => '0') MEM_BE
slv5 :=( others => '0') BTN
slv16 := x"0104" sysid_proj
slv20 :=( others => '0') MEM_ADDR
in VPWRP slv4 :=( others => '0')
in VPWRN slv4 :=( others => '0')
RB_ADDR slv16 := slv( to_unsigned( 2#0000000000000000#, 16) )
out MEM_ADDR slv( AWIDTH- 1 downto 0)