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W11 CPU core and support modules
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sys_tst_rlink_n4.vhd
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1-- $Id: sys_tst_rlink_n4.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_tst_rlink_n4 - syn
7-- Description: rlink tester design for nexys4
8--
9-- Dependencies: vlib/xlib/s7_cmt_sfs
10-- vlib/genlib/clkdivce
11-- bplib/bpgen/bp_rs232_4line_iob
12-- bplib/bpgen/sn_humanio_rbus
13-- vlib/rlink/rlink_sp1c
14-- rbd_tst_rlink
15-- bplib/bpgen/rgbdrv_master
16-- bplib/bpgen/rgbdrv_analog_rbus
17-- bplib/sysmon/sysmonx_rbus_base
18-- vlib/rbus/rbd_usracc
19-- vlib/rbus/rb_sres_or_2
20-- vlib/rbus/rb_sres_or_6
21--
22-- Test bench: tb/tb_tst_rlink_n4
23--
24-- Target Devices: generic
25-- Tool versions: viv 2014.4-2018.3; ghdl 0.29-0.35 (ise 14.5-14.7 retired)
26--
27-- Synthesized:
28-- Date Rev viv Target flop lutl lutm bram slic
29-- 2019-02-02 1108 2018.3 xc7a100t-1 1179 1725 36 3.0 606
30-- 2019-02-02 1108 2017.2 xc7a100t-1 1179 1813 36 3.0 627
31-- 2016-04-02 758 2015.4 xc7a100t-1 1113 1461 36 3.0 528 usracc
32-- 2016-03-27 753 2015.4 xc7a100t-1 1124 1461 36 3.0 522 meminf
33-- 2016-03-13 743 2015.4 xc7a100t-1 1124 1463 64 4.5 567 +XADC
34-- 2016-02-20 734 2015.4 xc7a100t-1 1080 1424 64 4.5 502 +RGB
35-- 2015-01-31 640 2014.4 xc7a100t-1 990 1360 64 4.5 495
36--
37-- Revision History:
38-- Date Rev Version Comment
39-- 2016-06-05 772 1.5.3 use CDUWIDTH=7, 120 MHz clock is natural choice
40-- 2016-04-02 758 1.5.2 add rbd_usracc_e2 (bitfile+jtag timestamp access)
41-- 2016-03-19 748 1.5.1 define rlink SYSID
42-- 2016-03-12 741 1.5 add sysmon_rbus
43-- 2016-02-20 734 1.4.2 add rgbdrv_analog_rbus for two rgb leds
44-- 2015-04-11 666 1.4.1 rearrange XON handling
45-- 2015-02-06 643 1.4 factor out memory
46-- 2015-02-01 641 1.3.1 separate I_BTNRST_N; autobaud on msb of display
47-- 2015-01-31 640 1.3 drop fusp iface; use new sn_hio
48-- 2014-11-09 603 1.2 use new rlink v4 iface and 4 bit STAT
49-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
50-- 2013-09-28 535 1.0 Initial version (derived from sys_tst_rlink_n3)
51------------------------------------------------------------------------------
52-- Usage of Nexys 4 Switches, Buttons, LEDs:
53--
54-- SWI(7:2): no function (only connected to sn_humanio_rbus)
55-- SWI(1): 1 enable XON
56-- SWI(0): -unused-
57--
58-- LED(7): SER_MONI.abact
59-- LED(6:2): no function (only connected to sn_humanio_rbus)
60-- LED(1): timer 1 busy
61-- LED(0): timer 0 busy
62--
63-- DSP: SER_MONI.clkdiv (from auto bauder)
64-- DP(3): not SER_MONI.txok (shows tx back pressure)
65-- DP(2): SER_MONI.txact (shows tx activity)
66-- DP(1): not SER_MONI.rxok (shows rx back pressure)
67-- DP(0): SER_MONI.rxact (shows rx activity)
68--
69
70library ieee;
71use ieee.std_logic_1164.all;
72
73use work.slvtypes.all;
74use work.xlib.all;
75use work.genlib.all;
76use work.serportlib.all;
77use work.rblib.all;
78use work.rbdlib.all;
79use work.rlinklib.all;
80use work.bpgenlib.all;
81use work.bpgenrbuslib.all;
82use work.sysmonrbuslib.all;
83use work.sys_conf.all;
84
85-- ----------------------------------------------------------------------------
86
87entity sys_tst_rlink_n4 is -- top level
88 -- implements nexys4_aif
89 port (
90 I_CLK100 : in slbit; -- 100 MHz clock
91 I_RXD : in slbit; -- receive data (board view)
92 O_TXD : out slbit; -- transmit data (board view)
93 O_RTS_N : out slbit; -- rx rts (board view; act.low)
94 I_CTS_N : in slbit; -- tx cts (board view; act.low)
95 I_SWI : in slv16; -- n4 switches
96 I_BTN : in slv5; -- n4 buttons
97 I_BTNRST_N : in slbit; -- n4 reset button
98 O_LED : out slv16; -- n4 leds
99 O_RGBLED0 : out slv3; -- n4 rgb-led 0
100 O_RGBLED1 : out slv3; -- n4 rgb-led 1
101 O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
102 O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
103 );
105
106architecture syn of sys_tst_rlink_n4 is
107
108 signal CLK : slbit := '0';
109
110 signal RXD : slbit := '1';
111 signal TXD : slbit := '0';
112 signal RTS_N : slbit := '0';
113 signal CTS_N : slbit := '0';
114
115 signal SWI : slv16 := (others=>'0');
116 signal BTN : slv5 := (others=>'0');
117 signal LED : slv16 := (others=>'0');
118 signal DSP_DAT : slv32 := (others=>'0');
119 signal DSP_DP : slv8 := (others=>'0');
120
121 signal RESET : slbit := '0';
122 signal CE_USEC : slbit := '0';
123 signal CE_MSEC : slbit := '0';
124
125 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
126 signal RB_SRES : rb_sres_type := rb_sres_init;
127 signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
128 signal RB_SRES_TST : rb_sres_type := rb_sres_init;
129 signal RB_SRES_RGB0 : rb_sres_type := rb_sres_init;
130 signal RB_SRES_RGB1 : rb_sres_type := rb_sres_init;
131 signal RB_SRES_RGB : rb_sres_type := rb_sres_init;
132 signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
133 signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
134
135 signal RB_LAM : slv16 := (others=>'0');
136 signal RB_STAT : slv4 := (others=>'0');
137
138 signal SER_MONI : serport_moni_type := serport_moni_init;
139 signal STAT : slv8 := (others=>'0');
140
141 signal RGBCNTL : slv3 := (others=>'0');
142 signal DIMCNTL : slv12 := (others=>'0');
143
144 constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
145 constant rbaddr_rgb0 : slv16 := x"fc00"; -- fe00/0004: 1111 1100 0000 00xx
146 constant rbaddr_rgb1 : slv16 := x"fc04"; -- fe04/0004: 1111 1100 0000 01xx
147 constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
148
149 constant sysid_proj : slv16 := x"0101"; -- tst_rlink
150 constant sysid_board : slv8 := x"05"; -- nexys4
151 constant sysid_vers : slv8 := x"00";
152
153begin
154
155 assert (sys_conf_clksys mod 1000000) = 0
156 report "assert sys_conf_clksys on MHz grid"
157 severity failure;
158
159 RESET <= '0'; -- so far not used
160
161 GEN_CLKSYS : s7_cmt_sfs
162 generic map (
163 VCO_DIVIDE => sys_conf_clksys_vcodivide,
164 VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
165 OUT_DIVIDE => sys_conf_clksys_outdivide,
166 CLKIN_PERIOD => 10.0,
167 CLKIN_JITTER => 0.01,
168 STARTUP_WAIT => false,
169 GEN_TYPE => sys_conf_clksys_gentype)
170 port map (
171 CLKIN => I_CLK100,
172 CLKFX => CLK,
173 LOCKED => open
174 );
175
176 CLKDIV : clkdivce
177 generic map (
178 CDUWIDTH => 7, -- good up to 127 MHz
179 USECDIV => sys_conf_clksys_mhz,
180 MSECDIV => 1000)
181 port map (
182 CLK => CLK,
183 CE_USEC => CE_USEC,
185 );
186
187 IOB_RS232 : bp_rs232_4line_iob
188 port map (
189 CLK => CLK,
190 RXD => RXD,
191 TXD => TXD,
192 CTS_N => CTS_N,
193 RTS_N => RTS_N,
194 I_RXD => I_RXD,
195 O_TXD => O_TXD,
196 I_CTS_N => I_CTS_N,
198 );
199
200 HIO : sn_humanio_rbus
201 generic map (
202 SWIDTH => 16,
203 BWIDTH => 5,
204 LWIDTH => 16,
205 DCWIDTH => 3,
206 DEBOUNCE => sys_conf_hio_debounce,
208 port map (
209 CLK => CLK,
210 RESET => RESET,
211 CE_MSEC => CE_MSEC,
212 RB_MREQ => RB_MREQ,
214 SWI => SWI,
215 BTN => BTN,
216 LED => LED,
217 DSP_DAT => DSP_DAT,
218 DSP_DP => DSP_DP,
219 I_SWI => I_SWI,
220 I_BTN => I_BTN,
221 O_LED => O_LED,
222 O_ANO_N => O_ANO_N,
224 );
225
226 RLINK : rlink_sp1c
227 generic map (
228 BTOWIDTH => 6,
229 RTAWIDTH => 12,
230 SYSID => sysid_proj & sysid_board & sysid_vers ,
231 IFAWIDTH => 5,
232 OFAWIDTH => 5,
233 ENAPIN_RLMON => sbcntl_sbf_rlmon,
234 ENAPIN_RBMON => sbcntl_sbf_rbmon,
235 CDWIDTH => 12,
236 CDINIT => sys_conf_ser2rri_cdinit,
237 RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink
238 RBMON_RBADDR => (others=>'0'))
239 port map (
240 CLK => CLK,
241 CE_USEC => CE_USEC,
242 CE_MSEC => CE_MSEC,
243 CE_INT => CE_MSEC,
244 RESET => RESET,
245 ENAXON => SWI(1),
246 ESCFILL => '0',
247 RXSD => RXD,
248 TXSD => TXD,
249 CTS_N => CTS_N,
250 RTS_N => RTS_N,
251 RB_MREQ => RB_MREQ,
252 RB_SRES => RB_SRES,
253 RB_LAM => RB_LAM,
254 RB_STAT => RB_STAT,
255 RL_MONI => open,
257 );
258
259 RBDTST : entity work.rbd_tst_rlink
260 port map (
261 CLK => CLK,
262 RESET => RESET,
263 CE_USEC => CE_USEC,
264 RB_MREQ => RB_MREQ,
266 RB_LAM => RB_LAM,
267 RB_STAT => RB_STAT,
269 RXSD => RXD,
270 RXACT => SER_MONI.rxact,
271 STAT => STAT
272 );
273
274 RGBMSTR : rgbdrv_master
275 generic map (
276 DWIDTH => DIMCNTL'length)
277 port map (
278 CLK => CLK,
279 RESET => RESET,
280 CE_USEC => CE_USEC,
281 RGBCNTL => RGBCNTL,
283 );
284
285 RGB0 : rgbdrv_analog_rbus
286 generic map (
287 DWIDTH => DIMCNTL'length,
289 port map (
290 CLK => CLK,
291 RESET => RESET,
292 RB_MREQ => RB_MREQ,
294 RGBCNTL => RGBCNTL,
295 DIMCNTL => DIMCNTL,
297 );
298
299 RGB1 : rgbdrv_analog_rbus
300 generic map (
301 DWIDTH => DIMCNTL'length,
303 port map (
304 CLK => CLK,
305 RESET => RESET,
306 RB_MREQ => RB_MREQ,
308 RGBCNTL => RGBCNTL,
309 DIMCNTL => DIMCNTL,
311 );
312
313
314 SMRB : if sys_conf_rbd_sysmon generate
316 generic map ( -- use default INIT_ (Vccint=1.00)
317 CLK_MHZ => sys_conf_clksys_mhz,
319 port map (
320 CLK => CLK,
321 RESET => RESET,
322 RB_MREQ => RB_MREQ,
324 ALM => open,
325 OT => open,
326 TEMP => open
327 );
328 end generate SMRB;
329
330 UARB : rbd_usracc
331 port map (
332 CLK => CLK,
333 RB_MREQ => RB_MREQ,
335 );
336
337 RB_SRES_ORRGB : rb_sres_or_2
338 port map (
342 );
343
344 RB_SRES_OR1 : rb_sres_or_6
345 port map (
352 );
353
354 DSP_DAT(31 downto 20) <= SER_MONI.abclkdiv(11 downto 0);
355 DSP_DAT(19) <= '0';
356 DSP_DAT(18 downto 16) <= SER_MONI.abclkdiv_f;
357 DSP_DP(7 downto 4) <= "0010";
358
359 DSP_DAT(15 downto 0) <= (others=>'0');
360
361 DSP_DP(3) <= not SER_MONI.txok;
362 DSP_DP(2) <= SER_MONI.txact;
363 DSP_DP(1) <= not SER_MONI.rxok;
364 DSP_DP(0) <= SER_MONI.rxact;
365
366 LED(15 downto 8) <= SWI(15 downto 8);
367 LED(7) <= SER_MONI.abact;
368 LED(6 downto 2) <= (others=>'0');
369 LED(1) <= STAT(1);
370 LED(0) <= STAT(0);
371
372end syn;
out CE_MSEC slbit
Definition: clkdivce.vhd:39
USECDIV positive := 50
Definition: clkdivce.vhd:33
CDUWIDTH positive := 6
Definition: clkdivce.vhd:32
out CE_USEC slbit
Definition: clkdivce.vhd:37
MSECDIV positive := 1000
Definition: clkdivce.vhd:34
in CLK slbit
Definition: clkdivce.vhd:36
in RB_SRES_2 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
in RB_SRES_2 rb_sres_type := rb_sres_init
in RB_SRES_3 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
in RB_SRES_4 rb_sres_type := rb_sres_init
in RB_SRES_5 rb_sres_type := rb_sres_init
in CLK slbit
Definition: rbd_usracc.vhd:40
in RB_MREQ rb_mreq_type
Definition: rbd_usracc.vhd:41
out RB_SRES rb_sres_type
Definition: rbd_usracc.vhd:43
Definition: rblib.vhd:32
RB_ADDR slv16 := x"0000"
in DIMCNTL slv( DWIDTH- 1 downto 0)
in RB_MREQ rb_mreq_type
out RB_SRES rb_sres_type
in RESET slbit := '0'
DWIDTH positive := 8
in CE_USEC slbit
in CLK slbit
in RESET slbit := '0'
out RGBCNTL slv3
out DIMCNTL slv( DWIDTH- 1 downto 0)
VCO_DIVIDE positive := 1
GEN_TYPE string := "PLL"
CLKIN_PERIOD real := 10.0
OUT_DIVIDE positive := 1
in CLKIN slbit
CLKIN_JITTER real := 0.01
STARTUP_WAIT boolean := false
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 11 downto 0) slv12
Definition: slvtypes.vhd:44
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
DEBOUNCE boolean := true
out O_LED slv( LWIDTH- 1 downto 0)
RB_ADDR slv16 := x"fef0"
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
DCWIDTH positive := 2
out SWI slv( SWIDTH- 1 downto 0)
in I_BTN slv( BWIDTH- 1 downto 0)
LWIDTH positive := 8
in I_SWI slv( SWIDTH- 1 downto 0)
SWIDTH positive := 8
out BTN slv( BWIDTH- 1 downto 0)
in RB_MREQ rb_mreq_type
BWIDTH positive := 4
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
out RB_SRES rb_sres_type
in LED slv( LWIDTH- 1 downto 0)
in RESET slbit := '0'
CLK_MHZ integer := 250
RB_ADDR slv16 := x"fb00"
in RB_MREQ rb_mreq_type
out RB_SRES rb_sres_type
in RESET slbit := '0'
Definition: xlib.vhd:35