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W11 CPU core and support modules
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sys_tst_rlink_arty.vhd
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1-- $Id: sys_tst_rlink_arty.vhd 1247 2022-07-06 07:04:33Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2016-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_tst_rlink_arty - syn
7-- Description: rlink tester design for arty board
8--
9-- Dependencies: vlib/xlib/s7_cmt_sfs
10-- vlib/genlib/clkdivce
11-- bplib/bpgen/bp_rs232_2line_iob
12-- bplib/bpgen/bp_swibtnled
13-- vlib/rlink/rlink_sp1c
14-- rbd_tst_rlink
15-- bplib/bpgen/rgbdrv_master
16-- bplib/bpgen/rgbdrv_analog_rbus
17-- bplib/sysmon/sysmonx_rbus_arty
18-- vlib/rbus/rbd_usracc
19-- vlib/rbus/rb_sres_or_4
20--
21-- Test bench: tb/tb_tst_rlink_arty
22--
23-- Target Devices: generic
24-- Tool versions: viv 2015.4-2022.1; ghdl 0.33-2.0.0
25--
26-- Synthesized (viv):
27-- Date Rev viv Target flop lutl lutm bram slic
28-- 2022-07-05 1247 2022.1 xc7a35t-1L 1033 1528 34 3.0 543
29-- 2019-02-02 1108 2018.3 xc7a35t-1L 1034 1613 36 3.0 550
30-- 2019-02-02 1108 2017.2 xc7a35t-1L 1036 1678 36 3.0 557
31-- 2017-06-05 907 2016.4 xc7a35t-1L 1033 1658 36 3.0 544
32-- 2016-03-27 753 2015.4 xc7a35t-1L 980 1396 36 3.0 494 meminf
33-- 2016-03-13 743 2015.4 xc7a35t-1L 980 1390 64 4.5 514 +XADC
34-- 2016-02-20 734 2015.4 xc7a35t-1L 941 1352 64 4.5 478
35-- 2016-02-14 731 2015.4 xc7a35t-1L 777 1313 64 4.5 399
36--
37-- Revision History:
38-- Date Rev Version Comment
39-- 2016-04-02 758 1.1.5 add rbd_usracc (bitfile+jtag timestamp access)
40-- 2016-03-19 748 1.1.4 define rlink SYSID
41-- 2016-03-13 743 1.1.3 hardwire XON=1, all SWI now unused
42-- 2016-03-12 741 1.1.2 use sysmonx_rbus_arty now
43-- 2016-03-06 740 1.1.1 add A_VPWRN/P to baseline config
44-- 2016-03-06 738 1.1 add xadc_rbus
45-- 2016-02-20 734 1.0.1 add rgbdrv_analog_rbus for four rgb leds
46-- 2016-02-14 731 1.0 Initial version (derived from sys_tst_rlink_b3)
47------------------------------------------------------------------------------
48-- Usage of Arty Switches, Buttons, LEDs:
49--
50-- SWI(3:2): no function
51-- SWI(1): -unused-
52-- SWI(0): -unused-
53--
54-- LED(3): not SER_MONI.txok (shows tx back pressure)
55-- LED(2): SER_MONI.txact (shows tx activity)
56-- LED(1): not SER_MONI.rxok (shows rx back pressure)
57-- LED(0): SER_MONI.rxact (shows rx activity)
58--
59
60library ieee;
61use ieee.std_logic_1164.all;
62
63use work.slvtypes.all;
64use work.xlib.all;
65use work.genlib.all;
66use work.serportlib.all;
67use work.rblib.all;
68use work.rbdlib.all;
69use work.rlinklib.all;
70use work.bpgenlib.all;
71use work.bpgenrbuslib.all;
72use work.sysmonrbuslib.all;
73use work.sys_conf.all;
74
75-- ----------------------------------------------------------------------------
76
77entity sys_tst_rlink_arty is -- top level
78 -- implements arty_aif
79 port (
80 I_CLK100 : in slbit; -- 100 MHz clock
81 I_RXD : in slbit; -- receive data (board view)
82 O_TXD : out slbit; -- transmit data (board view)
83 I_SWI : in slv4; -- arty switches
84 I_BTN : in slv4; -- arty buttons
85 O_LED : out slv4; -- arty leds
86 O_RGBLED0 : out slv3; -- arty rgb-led 0
87 O_RGBLED1 : out slv3; -- arty rgb-led 1
88 O_RGBLED2 : out slv3; -- arty rgb-led 2
89 O_RGBLED3 : out slv3; -- arty rgb-led 3
90 A_VPWRP : in slv4; -- arty pwrmon (pos)
91 A_VPWRN : in slv4 -- arty pwrmon (neg)
92 );
94
95architecture syn of sys_tst_rlink_arty is
96
97 signal CLK : slbit := '0';
98
99 signal RXD : slbit := '1';
100 signal TXD : slbit := '0';
101
102 signal SWI : slv4 := (others=>'0');
103 signal BTN : slv4 := (others=>'0');
104 signal LED : slv4 := (others=>'0');
105
106 signal RESET : slbit := '0';
107 signal CE_USEC : slbit := '0';
108 signal CE_MSEC : slbit := '0';
109
110 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
111 signal RB_SRES : rb_sres_type := rb_sres_init;
112 signal RB_SRES_TST : rb_sres_type := rb_sres_init;
113 signal RB_SRES_RGB : rb_sres_type := rb_sres_init;
114 signal RB_SRES_RGB0 : rb_sres_type := rb_sres_init;
115 signal RB_SRES_RGB1 : rb_sres_type := rb_sres_init;
116 signal RB_SRES_RGB2 : rb_sres_type := rb_sres_init;
117 signal RB_SRES_RGB3 : rb_sres_type := rb_sres_init;
118 signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
119 signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
120
121 signal RB_LAM : slv16 := (others=>'0');
122 signal RB_STAT : slv4 := (others=>'0');
123
124 signal SER_MONI : serport_moni_type := serport_moni_init;
125 signal STAT : slv8 := (others=>'0');
126
127 signal RGBCNTL : slv3 := (others=>'0');
128 signal DIMCNTL : slv12 := (others=>'0');
129
130 constant rbaddr_rgb0 : slv16 := x"fc00"; -- fe00/0004: 1111 1100 0000 00xx
131 constant rbaddr_rgb1 : slv16 := x"fc04"; -- fe04/0004: 1111 1100 0000 01xx
132 constant rbaddr_rgb2 : slv16 := x"fc08"; -- fe08/0004: 1111 1100 0000 10xx
133 constant rbaddr_rgb3 : slv16 := x"fc0c"; -- fe0c/0004: 1111 1100 0000 11xx
134 constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
135
136 constant sysid_proj : slv16 := x"0101"; -- tst_rlink
137 constant sysid_board : slv8 := x"07"; -- arty
138 constant sysid_vers : slv8 := x"00";
139
140begin
141
142 assert (sys_conf_clksys mod 1000000) = 0
143 report "assert sys_conf_clksys on MHz grid"
144 severity failure;
145
146 RESET <= '0'; -- so far not used
147
148 GEN_CLKSYS : s7_cmt_sfs
149 generic map (
150 VCO_DIVIDE => sys_conf_clksys_vcodivide,
151 VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
152 OUT_DIVIDE => sys_conf_clksys_outdivide,
153 CLKIN_PERIOD => 10.0,
154 CLKIN_JITTER => 0.01,
155 STARTUP_WAIT => false,
156 GEN_TYPE => sys_conf_clksys_gentype)
157 port map (
158 CLKIN => I_CLK100,
159 CLKFX => CLK,
160 LOCKED => open
161 );
162
163 CLKDIV : clkdivce
164 generic map (
165 CDUWIDTH => 7,
166 USECDIV => sys_conf_clksys_mhz,
167 MSECDIV => 1000)
168 port map (
169 CLK => CLK,
170 CE_USEC => CE_USEC,
172 );
173
174 IOB_RS232 : bp_rs232_2line_iob
175 port map (
176 CLK => CLK,
177 RXD => RXD,
178 TXD => TXD,
179 I_RXD => I_RXD,
180 O_TXD => O_TXD
181 );
182
183 HIO : bp_swibtnled
184 generic map (
185 SWIDTH => I_SWI'length,
186 BWIDTH => I_BTN'length,
187 LWIDTH => O_LED'length,
188 DEBOUNCE => sys_conf_hio_debounce)
189 port map (
190 CLK => CLK,
191 RESET => RESET,
192 CE_MSEC => CE_MSEC,
193 SWI => SWI,
194 BTN => BTN,
195 LED => LED,
196 I_SWI => I_SWI,
197 I_BTN => I_BTN,
198 O_LED => O_LED
199 );
200
201 RLINK : rlink_sp1c
202 generic map (
203 BTOWIDTH => 6,
204 RTAWIDTH => 12,
205 SYSID => sysid_proj & sysid_board & sysid_vers ,
206 IFAWIDTH => 5,
207 OFAWIDTH => 5,
208 ENAPIN_RLMON => sbcntl_sbf_rlmon,
209 ENAPIN_RBMON => sbcntl_sbf_rbmon,
210 CDWIDTH => 12,
211 CDINIT => sys_conf_ser2rri_cdinit,
212 RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink
213 RBMON_RBADDR => (others=>'0'))
214 port map (
215 CLK => CLK,
216 CE_USEC => CE_USEC,
217 CE_MSEC => CE_MSEC,
218 CE_INT => CE_MSEC,
219 RESET => RESET,
220 ENAXON => '1',
221 ESCFILL => '0',
222 RXSD => RXD,
223 TXSD => TXD,
224 CTS_N => '0',
225 RTS_N => open,
226 RB_MREQ => RB_MREQ,
227 RB_SRES => RB_SRES,
228 RB_LAM => RB_LAM,
229 RB_STAT => RB_STAT,
230 RL_MONI => open,
232 );
233
234 RBDTST : entity work.rbd_tst_rlink
235 port map (
236 CLK => CLK,
237 RESET => RESET,
238 CE_USEC => CE_USEC,
239 RB_MREQ => RB_MREQ,
241 RB_LAM => RB_LAM,
242 RB_STAT => RB_STAT,
244 RXSD => RXD,
245 RXACT => SER_MONI.rxact,
246 STAT => STAT
247 );
248
249 RGBMSTR : rgbdrv_master
250 generic map (
251 DWIDTH => DIMCNTL'length)
252 port map (
253 CLK => CLK,
254 RESET => RESET,
255 CE_USEC => CE_USEC,
256 RGBCNTL => RGBCNTL,
258 );
259
260 RGB0 : rgbdrv_analog_rbus
261 generic map (
262 DWIDTH => DIMCNTL'length,
264 port map (
265 CLK => CLK,
266 RESET => RESET,
267 RB_MREQ => RB_MREQ,
269 RGBCNTL => RGBCNTL,
270 DIMCNTL => DIMCNTL,
272 );
273
274 RGB1 : rgbdrv_analog_rbus
275 generic map (
276 DWIDTH => DIMCNTL'length,
278 port map (
279 CLK => CLK,
280 RESET => RESET,
281 RB_MREQ => RB_MREQ,
283 RGBCNTL => RGBCNTL,
284 DIMCNTL => DIMCNTL,
286 );
287
288 RGB2 : rgbdrv_analog_rbus
289 generic map (
290 DWIDTH => DIMCNTL'length,
292 port map (
293 CLK => CLK,
294 RESET => RESET,
295 RB_MREQ => RB_MREQ,
297 RGBCNTL => RGBCNTL,
298 DIMCNTL => DIMCNTL,
300 );
301
302 RGB3 : rgbdrv_analog_rbus
303 generic map (
304 DWIDTH => DIMCNTL'length,
306 port map (
307 CLK => CLK,
308 RESET => RESET,
309 RB_MREQ => RB_MREQ,
311 RGBCNTL => RGBCNTL,
312 DIMCNTL => DIMCNTL,
314 );
315
316 SMRB : if sys_conf_rbd_sysmon generate
318 generic map ( -- use default INIT_ (LP: Vccint=0.95)
319 CLK_MHZ => sys_conf_clksys_mhz,
321 port map (
322 CLK => CLK,
323 RESET => RESET,
324 RB_MREQ => RB_MREQ,
326 ALM => open,
327 OT => open,
328 TEMP => open,
329 VPWRN => A_VPWRN,
330 VPWRP => A_VPWRP
331 );
332 end generate SMRB;
333
334 RB_SRES_ORRGB : rb_sres_or_4
335 port map (
341 );
342
343 UARB : rbd_usracc
344 port map (
345 CLK => CLK,
346 RB_MREQ => RB_MREQ,
348 );
349
350 RB_SRES_OR1 : rb_sres_or_4
351 port map (
357 );
358
359 LED(3) <= not SER_MONI.txok;
360 LED(2) <= SER_MONI.txact;
361 LED(1) <= not SER_MONI.rxok;
362 LED(0) <= SER_MONI.rxact;
363
364end syn;
DEBOUNCE boolean := true
SWIDTH positive := 4
out O_LED slv( LWIDTH- 1 downto 0)
out SWI slv( SWIDTH- 1 downto 0)
in I_BTN slv( BWIDTH- 1 downto 0)
LWIDTH positive := 4
in I_SWI slv( SWIDTH- 1 downto 0)
out BTN slv( BWIDTH- 1 downto 0)
in CLK slbit
BWIDTH positive := 4
in LED slv( LWIDTH- 1 downto 0)
in RESET slbit := '0'
in CE_MSEC slbit
out CE_MSEC slbit
Definition: clkdivce.vhd:39
USECDIV positive := 50
Definition: clkdivce.vhd:33
CDUWIDTH positive := 6
Definition: clkdivce.vhd:32
out CE_USEC slbit
Definition: clkdivce.vhd:37
MSECDIV positive := 1000
Definition: clkdivce.vhd:34
in CLK slbit
Definition: clkdivce.vhd:36
in RB_SRES_2 rb_sres_type := rb_sres_init
in RB_SRES_3 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
in RB_SRES_4 rb_sres_type := rb_sres_init
in CLK slbit
Definition: rbd_usracc.vhd:40
in RB_MREQ rb_mreq_type
Definition: rbd_usracc.vhd:41
out RB_SRES rb_sres_type
Definition: rbd_usracc.vhd:43
Definition: rblib.vhd:32
RB_ADDR slv16 := x"0000"
in DIMCNTL slv( DWIDTH- 1 downto 0)
in RB_MREQ rb_mreq_type
out RB_SRES rb_sres_type
in RESET slbit := '0'
DWIDTH positive := 8
in CE_USEC slbit
in CLK slbit
in RESET slbit := '0'
out RGBCNTL slv3
out DIMCNTL slv( DWIDTH- 1 downto 0)
VCO_DIVIDE positive := 1
GEN_TYPE string := "PLL"
CLKIN_PERIOD real := 10.0
OUT_DIVIDE positive := 1
in CLKIN slbit
CLKIN_JITTER real := 0.01
STARTUP_WAIT boolean := false
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 11 downto 0) slv12
Definition: slvtypes.vhd:44
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
in VPWRP slv4 :=( others => '0')
CLK_MHZ integer := 250
RB_ADDR slv16 := x"fb00"
in RB_MREQ rb_mreq_type
out RB_SRES rb_sres_type
in VPWRN slv4 :=( others => '0')
in RESET slbit := '0'
Definition: xlib.vhd:35