44use ieee.std_logic_1164.
all;
85 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
86 signal RB_SRES : rb_sres_type := rb_sres_init;
95 signal SER_MONI : serport_moni_type := serport_moni_init;
110 assert (sys_conf_clksys mod 1000000) = 0
111 report "assert sys_conf_clksys on MHz grid"
124 GEN_TYPE => sys_conf_clksys_gentype
)
134 USECDIV => sys_conf_clksys_mhz,
155 SYSID => sysid_proj & sysid_board & sysid_vers ,
161 CDINIT => sys_conf_ser2rri_cdinit,
195 RXACT => SER_MONI.rxact,
225 SMRB : if sys_conf_rbd_sysmon generate
228 CLK_MHZ => sys_conf_clksys_mhz,
258 generic map (
DWIDTH => O_LED'length
)
out PAD slv( DWIDTH- 1 downto 0)
in DO slv( DWIDTH- 1 downto 0)
in RB_SRES_2 rb_sres_type := rb_sres_init
in RB_SRES_3 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
in RB_SRES_4 rb_sres_type := rb_sres_init
in RB_SRES_TOP rb_sres_type
in DIMCNTL slv( DWIDTH- 1 downto 0)
out DIMCNTL slv( DWIDTH- 1 downto 0)
ENAPIN_RBMON integer :=- 1
out SER_MONI serport_moni_type
ENAPIN_RLMON integer :=- 1
RBMON_RBADDR slv16 := rbaddr_rbmon
RBMON_AWIDTH natural := 0
SYSID slv32 :=( others => '0')
CLKIN_PERIOD real := 10.0
CLKIN_JITTER real := 0.01
STARTUP_WAIT boolean := false
VCO_MULTIPLY positive := 1
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 11 downto 0) slv12
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2
slv2 :=( others => '0') LED
slv8 := x"09" sysid_board
slv4 :=( others => '0') RB_STAT
rb_sres_type := rb_sres_init RB_SRES_SYSMON
slv3 :=( others => '0') RGBCNTL
rb_mreq_type := rb_mreq_init RB_MREQ
serport_moni_type := serport_moni_init SER_MONI
slv12 :=( others => '0') DIMCNTL
rb_sres_type := rb_sres_init RB_SRES
rb_sres_type := rb_sres_init RB_SRES_TST
slv16 := x"fc00" rbaddr_rgb0
slv16 := x"fb00" rbaddr_sysmon
rb_sres_type := rb_sres_init RB_SRES_USRACC
slv16 :=( others => '0') RB_LAM
slv8 :=( others => '0') STAT
rb_sres_type := rb_sres_init RB_SRES_RGB0
slv16 := x"0101" sysid_proj