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W11 CPU core and support modules
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sys_tst_rlink_c7.vhd
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1-- $Id: sys_tst_rlink_c7.vhd 1247 2022-07-06 07:04:33Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2017-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_tst_rlink_c7 - syn
7-- Description: rlink tester design for CmodA7 board
8--
9-- Dependencies: vlib/xlib/s7_cmt_sfs
10-- vlib/genlib/clkdivce
11-- bplib/bpgen/bp_rs232_2line_iob
12-- vlib/rlink/rlink_sp1c
13-- rbd_tst_rlink
14-- bplib/bpgen/rgbdrv_master
15-- bplib/bpgen/rgbdrv_analog_rbus
16-- bplib/sysmon/sysmonx_rbus_base
17-- vlib/rbus/rbd_usracc
18-- vlib/rbus/rb_sres_or_4
19-- vlib/xlib/iob_reg_o_gen
20--
21-- Test bench: tb/tb_tst_rlink_c7
22--
23-- Target Devices: generic
24-- Tool versions: viv 2016.4-2022.1; ghdl 0.34-2.0.0
25--
26-- Synthesized (viv):
27-- Date Rev viv Target flop lutl lutm bram slic
28-- 2022-07-05 1247 2022.1 xc7a35t-1 913 1402 34 3.0 494
29-- 2019-02-02 1108 2018.3 xc7a35t-1 913 1494 36 3.0 496
30-- 2019-02-02 1108 2017.2 xc7a35t-1 914 1581 36 3.0 510
31-- 2017-06-05 907 2016.4 xc7a35t-1 913 1556 36 3.0 513
32--
33-- Revision History:
34-- Date Rev Version Comment
35-- 2017-06-04 906 1.0 Initial version (derived from sys_tst_rlink_arty)
36------------------------------------------------------------------------------
37-- Usage of CmodA7 Buttons, LEDs, RGBLEDs:
38--
39-- LED(1): SER_MONI.txact (shows tx activity)
40-- LED(0): SER_MONI.rxact (shows rx activity)
41--
42
43library ieee;
44use ieee.std_logic_1164.all;
45
46use work.slvtypes.all;
47use work.xlib.all;
48use work.genlib.all;
49use work.serportlib.all;
50use work.rblib.all;
51use work.rbdlib.all;
52use work.rlinklib.all;
53use work.bpgenlib.all;
54use work.bpgenrbuslib.all;
55use work.sysmonrbuslib.all;
56use work.sys_conf.all;
57
58-- ----------------------------------------------------------------------------
59
60entity sys_tst_rlink_c7 is -- top level
61 -- implements cmoda7_aif
62 port (
63 I_CLK12 : in slbit; -- 12 MHz clock
64 I_RXD : in slbit; -- receive data (board view)
65 O_TXD : out slbit; -- transmit data (board view)
66 I_BTN : in slv2; -- c7 buttons
67 O_LED : out slv2; -- c7 leds
68 O_RGBLED0_N : out slv3 -- c7 rgb-led 0
69 );
71
72architecture syn of sys_tst_rlink_c7 is
73
74 signal CLK : slbit := '0';
75
76 signal RXD : slbit := '1';
77 signal TXD : slbit := '0';
78
79 signal LED : slv2 := (others=>'0');
80
81 signal RESET : slbit := '0';
82 signal CE_USEC : slbit := '0';
83 signal CE_MSEC : slbit := '0';
84
85 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
86 signal RB_SRES : rb_sres_type := rb_sres_init;
87 signal RB_SRES_TST : rb_sres_type := rb_sres_init;
88 signal RB_SRES_RGB0 : rb_sres_type := rb_sres_init;
89 signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
90 signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
91
92 signal RB_LAM : slv16 := (others=>'0');
93 signal RB_STAT : slv4 := (others=>'0');
94
95 signal SER_MONI : serport_moni_type := serport_moni_init;
96 signal STAT : slv8 := (others=>'0');
97
98 signal RGBCNTL : slv3 := (others=>'0');
99 signal DIMCNTL : slv12 := (others=>'0');
100
101 constant rbaddr_rgb0 : slv16 := x"fc00"; -- fe00/0004: 1111 1100 0000 00xx
102 constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
103
104 constant sysid_proj : slv16 := x"0101"; -- tst_rlink
105 constant sysid_board : slv8 := x"09"; -- cmoda7
106 constant sysid_vers : slv8 := x"00";
107
108begin
109
110 assert (sys_conf_clksys mod 1000000) = 0
111 report "assert sys_conf_clksys on MHz grid"
112 severity failure;
113
114 RESET <= '0'; -- so far not used
115
116 GEN_CLKSYS : s7_cmt_sfs
117 generic map (
118 VCO_DIVIDE => sys_conf_clksys_vcodivide,
119 VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
120 OUT_DIVIDE => sys_conf_clksys_outdivide,
121 CLKIN_PERIOD => 83.3,
122 CLKIN_JITTER => 0.01,
123 STARTUP_WAIT => false,
124 GEN_TYPE => sys_conf_clksys_gentype)
125 port map (
126 CLKIN => I_CLK12,
127 CLKFX => CLK,
128 LOCKED => open
129 );
130
131 CLKDIV : clkdivce
132 generic map (
133 CDUWIDTH => 7,
134 USECDIV => sys_conf_clksys_mhz,
135 MSECDIV => 1000)
136 port map (
137 CLK => CLK,
138 CE_USEC => CE_USEC,
140 );
141
142 IOB_RS232 : bp_rs232_2line_iob
143 port map (
144 CLK => CLK,
145 RXD => RXD,
146 TXD => TXD,
147 I_RXD => I_RXD,
148 O_TXD => O_TXD
149 );
150
151 RLINK : rlink_sp1c
152 generic map (
153 BTOWIDTH => 6,
154 RTAWIDTH => 12,
155 SYSID => sysid_proj & sysid_board & sysid_vers ,
156 IFAWIDTH => 5,
157 OFAWIDTH => 5,
158 ENAPIN_RLMON => sbcntl_sbf_rlmon,
159 ENAPIN_RBMON => sbcntl_sbf_rbmon,
160 CDWIDTH => 12,
161 CDINIT => sys_conf_ser2rri_cdinit,
162 RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink
163 RBMON_RBADDR => (others=>'0'))
164 port map (
165 CLK => CLK,
166 CE_USEC => CE_USEC,
167 CE_MSEC => CE_MSEC,
168 CE_INT => CE_MSEC,
169 RESET => RESET,
170 ENAXON => '1',
171 ESCFILL => '0',
172 RXSD => RXD,
173 TXSD => TXD,
174 CTS_N => '0',
175 RTS_N => open,
176 RB_MREQ => RB_MREQ,
177 RB_SRES => RB_SRES,
178 RB_LAM => RB_LAM,
179 RB_STAT => RB_STAT,
180 RL_MONI => open,
182 );
183
184 RBDTST : entity work.rbd_tst_rlink
185 port map (
186 CLK => CLK,
187 RESET => RESET,
188 CE_USEC => CE_USEC,
189 RB_MREQ => RB_MREQ,
191 RB_LAM => RB_LAM,
192 RB_STAT => RB_STAT,
194 RXSD => RXD,
195 RXACT => SER_MONI.rxact,
196 STAT => STAT
197 );
198
199 RGBMSTR : rgbdrv_master
200 generic map (
201 DWIDTH => DIMCNTL'length)
202 port map (
203 CLK => CLK,
204 RESET => RESET,
205 CE_USEC => CE_USEC,
206 RGBCNTL => RGBCNTL,
208 );
209
210 RGB0 : rgbdrv_analog_rbus
211 generic map (
212 DWIDTH => DIMCNTL'length,
213 ACTLOW => '1', -- CmodA7 has active low RGBLED
215 port map (
216 CLK => CLK,
217 RESET => RESET,
218 RB_MREQ => RB_MREQ,
220 RGBCNTL => RGBCNTL,
221 DIMCNTL => DIMCNTL,
223 );
224
225 SMRB : if sys_conf_rbd_sysmon generate
227 generic map ( -- use default INIT_ (LP: Vccint=0.95)
228 CLK_MHZ => sys_conf_clksys_mhz,
230 port map (
231 CLK => CLK,
232 RESET => RESET,
233 RB_MREQ => RB_MREQ,
235 ALM => open,
236 OT => open,
237 TEMP => open
238 );
239 end generate SMRB;
240
241 UARB : rbd_usracc
242 port map (
243 CLK => CLK,
244 RB_MREQ => RB_MREQ,
246 );
247
248 RB_SRES_OR1 : rb_sres_or_4
249 port map (
255 );
256
257 IOB_LED : iob_reg_o_gen
258 generic map (DWIDTH => O_LED'length)
259 port map (CLK => CLK, CE => '1', DO => LED, PAD => O_LED);
260
261 LED(1) <= SER_MONI.txact;
262 LED(0) <= SER_MONI.rxact;
263
264end syn;
out CE_MSEC slbit
Definition: clkdivce.vhd:39
USECDIV positive := 50
Definition: clkdivce.vhd:33
CDUWIDTH positive := 6
Definition: clkdivce.vhd:32
out CE_USEC slbit
Definition: clkdivce.vhd:37
MSECDIV positive := 1000
Definition: clkdivce.vhd:34
in CLK slbit
Definition: clkdivce.vhd:36
in CE slbit := '1'
out PAD slv( DWIDTH- 1 downto 0)
in CLK slbit
in DO slv( DWIDTH- 1 downto 0)
DWIDTH positive := 16
in RB_SRES_2 rb_sres_type := rb_sres_init
in RB_SRES_3 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
in RB_SRES_4 rb_sres_type := rb_sres_init
in CLK slbit
Definition: rbd_usracc.vhd:40
in RB_MREQ rb_mreq_type
Definition: rbd_usracc.vhd:41
out RB_SRES rb_sres_type
Definition: rbd_usracc.vhd:43
Definition: rblib.vhd:32
RB_ADDR slv16 := x"0000"
in DIMCNTL slv( DWIDTH- 1 downto 0)
in RB_MREQ rb_mreq_type
out RB_SRES rb_sres_type
in RESET slbit := '0'
DWIDTH positive := 8
in CE_USEC slbit
in CLK slbit
in RESET slbit := '0'
out RGBCNTL slv3
out DIMCNTL slv( DWIDTH- 1 downto 0)
VCO_DIVIDE positive := 1
GEN_TYPE string := "PLL"
CLKIN_PERIOD real := 10.0
OUT_DIVIDE positive := 1
in CLKIN slbit
CLKIN_JITTER real := 0.01
STARTUP_WAIT boolean := false
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 11 downto 0) slv12
Definition: slvtypes.vhd:44
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
CLK_MHZ integer := 250
RB_ADDR slv16 := x"fb00"
in RB_MREQ rb_mreq_type
out RB_SRES rb_sres_type
in RESET slbit := '0'
Definition: xlib.vhd:35