w11 - vhd 0.794
W11 CPU core and support modules
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sys_w11a_br_n4d.vhd
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1-- $Id: sys_w11a_br_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2017-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_w11a_br_n4d - syn
7-- Description: w11a test design for nexys4d (bram only)
8--
9-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce
10-- bplib/bpgen/bp_rs232_4line_iob
11-- vlib/rlink/rlink_sp2c
12-- w11a/pdp11_sys70
13-- ibus/ibdr_maxisys
14-- w11a/pdp11_bram_memctl
15-- vlib/rlink/ioleds_sp1c
16-- w11a/pdp11_hio70
17-- bplib/bpgen/sn_humanio_rbus
18-- bplib/sysmon/sysmonx_rbus_base
19-- vlib/rbus/rbd_usracc
20-- vlib/rbus/rb_sres_or_4
21--
22-- Test bench: tb/tb_sys_w11a_br_n4d
23--
24-- Target Devices: generic
25-- Tool versions: viv 2016.2-2022.1; ghdl 0.34-2.0.0
26--
27-- Synthesized:
28-- Date Rev viv Target flop lutl lutm bram slic
29-- 2022-07-05 1247 2022.1 xc7a100t-1 3099 5842 267 132.0 1957
30-- 2019-05-19 1150 2017.2 xc7a100t-1 3097 6562 273 132.0 2110 +dz11
31-- 2019-02-02 1108 2018.3 xc7a100t-1 2837 6083 170 131.5 1957
32-- 2019-02-02 1108 2017.2 xc7a100t-1 2825 5843 170 131.5 1824 +dmpcnt
33-- 2018-09-15 1045 2017.2 xc7a100t-1 2602 5490 138 131.5 1754 +KW11P
34-- 2017-05-25 898 2016.4 xc7a100t-1 2541 5500 138 131.5 1750 +DEUNA
35-- 2017-01-07 842 2016.4 xc7a100t-1 2491 5335 138 131.5 1728
36--
37-- Revision History:
38-- Date Rev Version Comment
39-- 2018-12-16 1086 1.2 use s7_cmt_1ce1ce
40-- 2018-10-13 1055 1.1 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
41-- 2017-01-04 838 1.0 Initial version (derived from sys_w11a_br_n4)
42------------------------------------------------------------------------------
43--
44-- w11a test design for nexys4d
45-- w11a + rlink + serport
46--
47-- Usage of Nexys 4DDR Switches, Buttons, LEDs
48--
49-- SWI(15:5): no function (only connected to sn_humanio_rbus)
50-- (5): select DSP(7:4) display
51-- 0 abclkdiv & abclkdiv_f
52-- 1 PC
53-- (4): select DSP(3:0) display
54-- 0 DISPREG
55-- 1 DR emulation
56-- (3): select LED display
57-- 0 overall status
58-- 1 DR emulation
59-- (2): unused-reserved (USB port select)
60-- (1): 1 enable XON
61-- (0): unused-reserved (serial port select)
62--
63-- LEDs if SWI(3) = 1
64-- (15:0) DR emulation; shows R0 during wait like 11/45+70
65--
66-- LEDs if SWI(3) = 0
67-- (7) MEM_ACT_W
68-- (6) MEM_ACT_R
69-- (5) cmdbusy (all rlink access, mostly rdma)
70-- (4:0) if cpugo=1 show cpu mode activity
71-- (4) kernel mode, pri>0
72-- (3) kernel mode, pri=0
73-- (2) kernel mode, wait
74-- (1) supervisor mode
75-- (0) user mode
76-- if cpugo=0 shows cpurust
77-- (4) '1'
78-- (3:0) cpurust code
79--
80-- DSP(7:4) shows abclkdiv & abclkdiv_f or PS, depending on SWI(5)
81-- DSP(3:0) shows DISPREG or DR emulation, depending on SWI(4)
82-- DP(3:0) shows IO activity
83-- (3) not SER_MONI.txok (shows tx back pressure)
84-- (2) SER_MONI.txact (shows tx activity)
85-- (1) not SER_MONI.rxok (shows rx back pressure)
86-- (0) SER_MONI.rxact (shows rx activity)
87--
88
89library ieee;
90use ieee.std_logic_1164.all;
91use ieee.numeric_std.all;
92
93use work.slvtypes.all;
94use work.serportlib.all;
95use work.rblib.all;
96use work.rbdlib.all;
97use work.rlinklib.all;
98use work.bpgenlib.all;
99use work.bpgenrbuslib.all;
100use work.sysmonrbuslib.all;
101use work.iblib.all;
102use work.ibdlib.all;
103use work.pdp11.all;
104use work.sys_conf.all;
105
106-- ----------------------------------------------------------------------------
107
108entity sys_w11a_br_n4d is -- top level
109 -- implements nexys4d_aif
110 port (
111 I_CLK100 : in slbit; -- 100 MHz clock
112 I_RXD : in slbit; -- receive data (board view)
113 O_TXD : out slbit; -- transmit data (board view)
114 O_RTS_N : out slbit; -- rx rts (board view; act.low)
115 I_CTS_N : in slbit; -- tx cts (board view; act.low)
116 I_SWI : in slv16; -- n4d switches
117 I_BTN : in slv5; -- n4d buttons
118 I_BTNRST_N : in slbit; -- n4d reset button
119 O_LED : out slv16; -- n4d leds
120 O_RGBLED0 : out slv3; -- n4d rgb-led 0
121 O_RGBLED1 : out slv3; -- n4d rgb-led 1
122 O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
123 O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
124 );
126
127architecture syn of sys_w11a_br_n4d is
128
129 signal CLK : slbit := '0';
130
131 signal RESET : slbit := '0';
132 signal CE_USEC : slbit := '0';
133 signal CE_MSEC : slbit := '0';
134
135 signal CLKS : slbit := '0';
136 signal CES_MSEC : slbit := '0';
137
138 signal RXD : slbit := '1';
139 signal TXD : slbit := '0';
140 signal RTS_N : slbit := '0';
141 signal CTS_N : slbit := '0';
142
143 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
144 signal RB_SRES : rb_sres_type := rb_sres_init;
145 signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
146 signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
147 signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
148 signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
149
150 signal RB_LAM : slv16 := (others=>'0');
151 signal RB_STAT : slv4 := (others=>'0');
152
153 signal SER_MONI : serport_moni_type := serport_moni_init;
154
155 signal SWI : slv16 := (others=>'0');
156 signal BTN : slv5 := (others=>'0');
157 signal LED : slv16 := (others=>'0');
158 signal DSP_DAT : slv32 := (others=>'0');
159 signal DSP_DP : slv8 := (others=>'0');
160
161 signal GRESET : slbit := '0'; -- general reset (from rbus)
162 signal CRESET : slbit := '0'; -- cpu reset (from cp)
163 signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
164 signal PERFEXT : slv8 := (others=>'0');
165
166 signal EI_PRI : slv3 := (others=>'0');
167 signal EI_VECT : slv9_2 := (others=>'0');
168 signal EI_ACKM : slbit := '0';
169
170 signal CP_STAT : cp_stat_type := cp_stat_init;
171 signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
172
173 signal MEM_REQ : slbit := '0';
174 signal MEM_WE : slbit := '0';
175 signal MEM_BUSY : slbit := '0';
176 signal MEM_ACK_R : slbit := '0';
177 signal MEM_ACT_R : slbit := '0';
178 signal MEM_ACT_W : slbit := '0';
179 signal MEM_ADDR : slv20 := (others=>'0');
180 signal MEM_BE : slv4 := (others=>'0');
181 signal MEM_DI : slv32 := (others=>'0');
182 signal MEM_DO : slv32 := (others=>'0');
183
184 signal IB_MREQ : ib_mreq_type := ib_mreq_init;
185 signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
186
187 signal DISPREG : slv16 := (others=>'0');
188 signal ABCLKDIV : slv16 := (others=>'0');
189
190 constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
191 constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
192 constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
193
194 constant sysid_proj : slv16 := x"0201"; -- w11a
195 constant sysid_board : slv8 := x"08"; -- nexys4d
196 constant sysid_vers : slv8 := x"00";
197
198begin
199
200 assert (sys_conf_clksys mod 1000000) = 0
201 report "assert sys_conf_clksys on MHz grid"
202 severity failure;
203
204 GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
205 generic map (
206 CLKIN_PERIOD => 10.0,
207 CLKIN_JITTER => 0.01,
208 STARTUP_WAIT => false,
209 CLK0_VCODIV => sys_conf_clksys_vcodivide,
210 CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
211 CLK0_OUTDIV => sys_conf_clksys_outdivide,
212 CLK0_GENTYPE => sys_conf_clksys_gentype,
213 CLK0_CDUWIDTH => 7,
214 CLK0_USECDIV => sys_conf_clksys_mhz,
215 CLK0_MSECDIV => 1000,
216 CLK1_VCODIV => sys_conf_clkser_vcodivide,
217 CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
218 CLK1_OUTDIV => sys_conf_clkser_outdivide,
219 CLK1_GENTYPE => sys_conf_clkser_gentype,
220 CLK1_CDUWIDTH => 7,
221 CLK1_USECDIV => sys_conf_clkser_mhz,
222 CLK1_MSECDIV => 1000)
223 port map (
224 CLKIN => I_CLK100,
225 CLK0 => CLK,
226 CE0_USEC => CE_USEC,
227 CE0_MSEC => CE_MSEC,
228 CLK1 => CLKS,
229 CE1_USEC => open,
230 CE1_MSEC => CES_MSEC,
231 LOCKED => open
232 );
233
234 IOB_RS232 : bp_rs232_4line_iob -- serport iob ----------------------
235 port map (
236 CLK => CLKS,
237 RXD => RXD,
238 TXD => TXD,
239 CTS_N => CTS_N,
240 RTS_N => RTS_N,
241 I_RXD => I_RXD,
242 O_TXD => O_TXD,
243 I_CTS_N => I_CTS_N,
244 O_RTS_N => O_RTS_N
245 );
246
247 RLINK : rlink_sp2c -- rlink for serport -----------------
248 generic map (
249 BTOWIDTH => 7, -- 128 cycles access timeout
250 RTAWIDTH => 12,
251 SYSID => sysid_proj & sysid_board & sysid_vers ,
252 IFAWIDTH => 5, -- 32 word input fifo
253 OFAWIDTH => 5, -- 32 word output fifo
254 ENAPIN_RLMON => sbcntl_sbf_rlmon,
255 ENAPIN_RBMON => sbcntl_sbf_rbmon,
256 CDWIDTH => 12,
257 CDINIT => sys_conf_ser2rri_cdinit,
258 RBMON_AWIDTH => sys_conf_rbmon_awidth,
259 RBMON_RBADDR => rbaddr_rbmon)
260 port map (
261 CLK => CLK,
262 CE_USEC => CE_USEC,
263 CE_MSEC => CE_MSEC,
264 CE_INT => CE_MSEC,
265 RESET => RESET,
266 CLKS => CLKS,
267 CES_MSEC => CES_MSEC,
268 ENAXON => SWI(1),
269 ESCFILL => '0',
270 RXSD => RXD,
271 TXSD => TXD,
272 CTS_N => CTS_N,
273 RTS_N => RTS_N,
274 RB_MREQ => RB_MREQ,
275 RB_SRES => RB_SRES,
276 RB_LAM => RB_LAM,
277 RB_STAT => RB_STAT,
278 RL_MONI => open,
279 SER_MONI => SER_MONI
280 );
281
282 PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
283 PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
284 PERFEXT(2) <= '0'; -- unused (ext_wrflush)
285 PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
286 PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
287 PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
288 PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
289 PERFEXT(7) <= CE_USEC; -- ext_usec
290
291 SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
292 port map (
293 CLK => CLK,
294 RESET => RESET,
295 RB_MREQ => RB_MREQ,
296 RB_SRES => RB_SRES_CPU,
297 RB_STAT => RB_STAT,
298 RB_LAM_CPU => RB_LAM(0),
299 GRESET => GRESET,
300 CRESET => CRESET,
301 BRESET => BRESET,
302 CP_STAT => CP_STAT,
303 EI_PRI => EI_PRI,
304 EI_VECT => EI_VECT,
305 EI_ACKM => EI_ACKM,
306 PERFEXT => PERFEXT,
307 IB_MREQ => IB_MREQ,
308 IB_SRES => IB_SRES_IBDR,
309 MEM_REQ => MEM_REQ,
310 MEM_WE => MEM_WE,
311 MEM_BUSY => MEM_BUSY,
312 MEM_ACK_R => MEM_ACK_R,
313 MEM_ADDR => MEM_ADDR,
314 MEM_BE => MEM_BE,
315 MEM_DI => MEM_DI,
316 MEM_DO => MEM_DO,
317 DM_STAT_EXP => DM_STAT_EXP
318 );
319
320 IBDR_SYS : ibdr_maxisys -- IO system -------------------------
321 port map (
322 CLK => CLK,
323 CE_USEC => CE_USEC,
324 CE_MSEC => CE_MSEC,
325 RESET => GRESET,
326 BRESET => BRESET,
327 ITIMER => DM_STAT_EXP.se_itimer,
328 IDEC => DM_STAT_EXP.se_idec,
329 CPUSUSP => CP_STAT.cpususp,
330 RB_LAM => RB_LAM(15 downto 1),
331 IB_MREQ => IB_MREQ,
332 IB_SRES => IB_SRES_IBDR,
333 EI_ACKM => EI_ACKM,
334 EI_PRI => EI_PRI,
335 EI_VECT => EI_VECT,
336 DISPREG => DISPREG
337 );
338
339 BRAM_CTL: pdp11_bram_memctl -- memory controller -----------------
340 generic map (
341 MAWIDTH => sys_conf_memctl_mawidth,
342 NBLOCK => sys_conf_memctl_nblock)
343 port map (
344 CLK => CLK,
345 RESET => GRESET,
346 REQ => MEM_REQ,
347 WE => MEM_WE,
348 BUSY => MEM_BUSY,
349 ACK_R => MEM_ACK_R,
350 ACK_W => open,
351 ACT_R => MEM_ACT_R,
352 ACT_W => MEM_ACT_W,
353 ADDR => MEM_ADDR,
354 BE => MEM_BE,
355 DI => MEM_DI,
356 DO => MEM_DO
357 );
358
359 LED_IO : ioleds_sp1c -- hio leds from serport -------------
360 port map (
361 SER_MONI => SER_MONI,
362 IOLEDS => DSP_DP(3 downto 0)
363 );
364 DSP_DP(7 downto 4) <= "0010";
365 ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
366
367 HIO70 : pdp11_hio70 -- hio from sys70 --------------------
368 generic map (
369 LWIDTH => LED'length,
370 DCWIDTH => 3)
371 port map (
372 SEL_LED => SWI(3),
373 SEL_DSP => SWI(5 downto 4),
374 MEM_ACT_R => MEM_ACT_R,
375 MEM_ACT_W => MEM_ACT_W,
376 CP_STAT => CP_STAT,
377 DM_STAT_EXP => DM_STAT_EXP,
378 ABCLKDIV => ABCLKDIV,
379 DISPREG => DISPREG,
380 LED => LED,
381 DSP_DAT => DSP_DAT
382 );
383
384 HIO : sn_humanio_rbus -- hio manager -----------------------
385 generic map (
386 SWIDTH => 16,
387 BWIDTH => 5,
388 LWIDTH => 16,
389 DCWIDTH => 3,
390 DEBOUNCE => sys_conf_hio_debounce,
391 RB_ADDR => rbaddr_hio)
392 port map (
393 CLK => CLK,
394 RESET => RESET,
395 CE_MSEC => CE_MSEC,
396 RB_MREQ => RB_MREQ,
397 RB_SRES => RB_SRES_HIO,
398 SWI => SWI,
399 BTN => BTN,
400 LED => LED,
401 DSP_DAT => DSP_DAT,
402 DSP_DP => DSP_DP,
403 I_SWI => I_SWI,
404 I_BTN => I_BTN,
405 O_LED => O_LED,
406 O_ANO_N => O_ANO_N,
407 O_SEG_N => O_SEG_N
408 );
409
410 SMRB : if sys_conf_rbd_sysmon generate
412 generic map ( -- use default INIT_ (Vccint=1.00)
413 CLK_MHZ => sys_conf_clksys_mhz,
415 port map (
416 CLK => CLK,
417 RESET => RESET,
418 RB_MREQ => RB_MREQ,
420 ALM => open,
421 OT => open,
422 TEMP => open
423 );
424 end generate SMRB;
425
426 UARB : rbd_usracc
427 port map (
428 CLK => CLK,
429 RB_MREQ => RB_MREQ,
431 );
432
433 RB_SRES_OR : rb_sres_or_4 -- rbus or ---------------------------
434 port map (
435 RB_SRES_1 => RB_SRES_CPU,
436 RB_SRES_2 => RB_SRES_HIO,
437 RB_SRES_3 => RB_SRES_SYSMON,
438 RB_SRES_4 => RB_SRES_USRACC,
439 RB_SRES_OR => RB_SRES
440 );
441
442 -- setup unused outputs in nexys4d
443 O_RGBLED0 <= (others=>'0');
444 O_RGBLED1 <= (others=>not I_BTNRST_N);
445
446end syn;
Definition: iblib.vhd:33
Definition: pdp11.vhd:123
in CLK slbit
Definition: rbd_usracc.vhd:40
in RB_MREQ rb_mreq_type
Definition: rbd_usracc.vhd:41
out RB_SRES rb_sres_type
Definition: rbd_usracc.vhd:43
Definition: rblib.vhd:32
std_logic_vector( 19 downto 0) slv20
Definition: slvtypes.vhd:53
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 8 downto 2) slv9_2
Definition: slvtypes.vhd:65
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
slv9_2 :=( others => '0') EI_VECT
slv8 :=( others => '0') PERFEXT
slv16 := x"ffe8" rbaddr_rbmon
slv16 := x"fef0" rbaddr_hio
slv16 :=( others => '0') DISPREG
slv32 :=( others => '0') DSP_DAT
ib_mreq_type := ib_mreq_init IB_MREQ
sn_humanio_rbus hiohio
slv3 :=( others => '0') EI_PRI
slv16 :=( others => '0') SWI
slv4 :=( others => '0') RB_STAT
slv8 := x"08" sysid_board
slv32 :=( others => '0') MEM_DI
rb_sres_type := rb_sres_init RB_SRES_SYSMON
rb_mreq_type := rb_mreq_init RB_MREQ
serport_moni_type := serport_moni_init SER_MONI
pdp11_sys70 sys70sys70
slv16 :=( others => '0') ABCLKDIV
slv32 :=( others => '0') MEM_DO
rlink_sp2c rlinkrlink
rb_sres_type := rb_sres_init RB_SRES
slv16 :=( others => '0') LED
cp_stat_type := cp_stat_init CP_STAT
slv8 := x"00" sysid_vers
rb_sres_type := rb_sres_init RB_SRES_CPU
slv16 := x"0201" sysid_proj
slv8 :=( others => '0') DSP_DP
slv16 := x"fb00" rbaddr_sysmon
ib_sres_type := ib_sres_init IB_SRES_IBDR
rb_sres_type := rb_sres_init RB_SRES_USRACC
slv16 :=( others => '0') RB_LAM
rb_sres_type := rb_sres_init RB_SRES_HIO
slv4 :=( others => '0') MEM_BE
slv5 :=( others => '0') BTN
dm_stat_exp_type := dm_stat_exp_init DM_STAT_EXP
slv20 :=( others => '0') MEM_ADDR
CLK_MHZ integer := 250
RB_ADDR slv16 := x"fb00"
in RB_MREQ rb_mreq_type
out RB_SRES rb_sres_type
in RESET slbit := '0'