w11 - vhd 0.794
W11 CPU core and support modules
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sys_w11a_as7.vhd
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1-- $Id: sys_w11a_as7.vhd 1247 2022-07-06 07:04:33Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2019-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_w11a_br_as7 - syn
7-- Description: w11a design for as7 (with dram via mig)
8--
9-- Dependencies: vlib/xlib/bufg_unisim
10-- bplib/bpgen/s7_cmt_1ce1ce2c
11-- cdclib/cdc_signal_s1_as
12-- bplib/bpgen/bp_rs232_2line_iob
13-- vlib/rlink/rlink_sp2c
14-- w11a/pdp11_sys70
15-- ibus/ibdr_maxisys
16-- bplib/artys7/sramif_mig_artys7
17-- vlib/rlink/ioleds_sp1c
18-- pdp11_hio70_artys7
19-- bplib/bpgen/bp_swibtnled
20-- bplib/bpgen/rgbdrv_3x2mux
21-- bplib/sysmon/sysmonx_rbus_base
22-- vlib/rbus/rbd_usracc
23-- vlib/rbus/rb_sres_or_3
24--
25-- Test bench: tb/tb_sys_w11a_as7
26--
27-- Target Devices: generic
28-- Tool versions: viv 2018.3-2022.1; ghdl 0.35-2.0.0
29--
30-- Synthesized:
31-- Date Rev viv Target flop lutl lutm bram slic
32-- 2022-07-05 1247 2022.1 xc7s50 6843 9162 878 17.5 3184
33-- 2019-05-19 1150 2018.3 xc7s50 6843 10554 926 17.5 3425 +dz11
34-- 2019-01-12 1105 2018.3 xc7s50 6585 9837 806 17.0 3250
35--
36-- Revision History:
37-- Date Rev Version Comment
38-- 2022-07-05 1247 1.0.1 use bufg_unisim
39-- 2019-01-12 1105 1.0 Initial version (derived from sys_w11a_arty/br_as7)
40------------------------------------------------------------------------------
41--
42-- w11a design for artys7 (using DDR3 memory via MIG)
43-- w11a + rlink + serport
44--
45-- Usage of Arty S7 switches, Buttons, LEDs
46--
47-- SWI(3:0): determine what is displayed in the LEDs and RGBLEDs
48-- 00xy LED shows IO
49-- y=1 enables CPU activities on RGB_G,RGB_R
50-- x=1 enables MEM activities on RGB_B
51-- 0100 LED+RGB give DR emulation 'light show'
52-- 1xyy LED+RGB show low (x=0) or high (x=1) byte of
53-- yy = 00: abclkdiv & abclkdiv_f
54-- 01: PC
55-- 10: DISPREG
56-- 11: DR emulation
57-- LED shows bit 7:4, RGB bit 1:0 of the byte selected by x
58--
59-- LED and RGB assignment for SWI=00xy
60-- LED IO activity
61-- (3) not SER_MONI.txok (shows tx back pressure)
62-- (2) SER_MONI.txact (shows tx activity)
63-- (1) not SER_MONI.rxok (shows rx back pressure)
64-- (0) SER_MONI.rxact (shows rx activity)
65-- RGB_G CPU busy (active cpugo=1, enabled with SWI(0))
66-- (1) kernel mode, non-wait
67-- (0) user or supervisor mode
68-- RGB_R CPU rust (active cpugo=0, enabled with SWI(0))
69-- (1:0) cpurust code
70-- RGB_B MEM/cmd busy (enabled with SWI(1))
71-- (1) cmdbusy (all rlink access, mostly rdma)
72-- (0) not cpugo
73--
74-- LED and RGB assignment for SWI=0100 (DR emulation)
75-- LED DR(15:12)
76-- RGB_B DR( 9:08)
77-- RGB_G DR( 5:04)
78-- RGB_R DR( 1:00)
79--
80
81library ieee;
82use ieee.std_logic_1164.all;
83use ieee.numeric_std.all;
84
85use work.slvtypes.all;
86use work.xlib.all;
87use work.cdclib.all;
88use work.serportlib.all;
89use work.rblib.all;
90use work.rbdlib.all;
91use work.rlinklib.all;
92use work.bpgenlib.all;
93use work.sysmonrbuslib.all;
94use work.miglib.all;
95use work.miglib_artys7.all;
96use work.iblib.all;
97use work.ibdlib.all;
98use work.pdp11.all;
99use work.sys_conf.all;
100
101-- ----------------------------------------------------------------------------
102
103entity sys_w11a_as7 is -- top level
104 -- implements artys7_dram_aif
105 port (
106 I_CLK100 : in slbit; -- 100 MHz clock
107 I_RXD : in slbit; -- receive data (board view)
108 O_TXD : out slbit; -- transmit data (board view)
109 I_SWI : in slv4; -- artys7 switches
110 I_BTN : in slv4; -- artys7 buttons
111 O_LED : out slv4; -- artys7 leds
112 O_RGBLED0 : out slv3; -- artys7 rgb-led 0
113 O_RGBLED1 : out slv3; -- artys7 rgb-led 1
114 DDR3_DQ : inout slv16; -- dram: data in/out
115 DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
116 DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
117 DDR3_ADDR : out slv14; -- dram: address
118 DDR3_BA : out slv3; -- dram: bank address
119 DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
120 DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
121 DDR3_WE_N : out slbit; -- dram: write enable (act.low)
122 DDR3_RESET_N : out slbit; -- dram: reset (act.low)
123 DDR3_CK_P : out slv1; -- dram: clock (diff-p)
124 DDR3_CK_N : out slv1; -- dram: clock (diff-n)
125 DDR3_CKE : out slv1; -- dram: clock enable
126 DDR3_CS_N : out slv1; -- dram: chip select (act.low)
127 DDR3_DM : out slv2; -- dram: data input mask
128 DDR3_ODT : out slv1 -- dram: on-die termination
129 );
130end sys_w11a_as7;
131
132architecture syn of sys_w11a_as7 is
133
134 signal CLK100_BUF : slbit := '0';
135
136 signal CLK : slbit := '0';
137
138 signal RESET : slbit := '0';
139 signal CE_USEC : slbit := '0';
140 signal CE_MSEC : slbit := '0';
141
142 signal CLKS : slbit := '0';
143 signal CES_MSEC : slbit := '0';
144
145 signal CLKMIG : slbit := '0';
146 signal CLKREF : slbit := '0';
147
148 signal LOCKED : slbit := '0'; -- raw LOCKED
149 signal LOCKED_CLK : slbit := '0'; -- sync'ed to CLK
150
151 signal GBL_RESET : slbit := '0';
152
153 signal RXD : slbit := '1';
154 signal TXD : slbit := '0';
155
156 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
157 signal RB_SRES : rb_sres_type := rb_sres_init;
158 signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
159 signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
160 signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
161
162 signal RB_LAM : slv16 := (others=>'0');
163 signal RB_STAT : slv4 := (others=>'0');
164
165 signal SER_MONI : serport_moni_type := serport_moni_init;
166
167 signal GRESET : slbit := '0'; -- general reset (from rbus)
168 signal CRESET : slbit := '0'; -- cpu reset (from cp)
169 signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
170 signal PERFEXT : slv8 := (others=>'0');
171
172 signal EI_PRI : slv3 := (others=>'0');
173 signal EI_VECT : slv9_2 := (others=>'0');
174 signal EI_ACKM : slbit := '0';
175 signal CP_STAT : cp_stat_type := cp_stat_init;
176 signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
177
178 signal MEM_REQ : slbit := '0';
179 signal MEM_WE : slbit := '0';
180 signal MEM_BUSY : slbit := '0';
181 signal MEM_ACK_R : slbit := '0';
182 signal MEM_ACT_R : slbit := '0';
183 signal MEM_ACT_W : slbit := '0';
184 signal MEM_ADDR : slv20 := (others=>'0');
185 signal MEM_BE : slv4 := (others=>'0');
186 signal MEM_DI : slv32 := (others=>'0');
187 signal MEM_DO : slv32 := (others=>'0');
188
189 signal MIG_MONI : sramif2migui_moni_type := sramif2migui_moni_init;
190
191 signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
192
193 signal IB_MREQ : ib_mreq_type := ib_mreq_init;
194 signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
195
196 signal DISPREG : slv16 := (others=>'0');
197 signal ABCLKDIV : slv16 := (others=>'0');
198 signal IOLEDS : slv4 := (others=>'0');
199
200 signal SWI : slv4 := (others=>'0');
201 signal BTN : slv4 := (others=>'0');
202 signal LED : slv4 := (others=>'0');
203 signal RGB_R : slv2 := (others=>'0');
204 signal RGB_G : slv2 := (others=>'0');
205 signal RGB_B : slv2 := (others=>'0');
206
207 constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
208 constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
209
210 constant sysid_proj : slv16 := x"0201"; -- w11a
211 constant sysid_board : slv8 := x"0a"; -- artys7
212 constant sysid_vers : slv8 := x"00";
213
214begin
215
216 assert (sys_conf_clksys mod 1000000) = 0
217 report "assert sys_conf_clksys on MHz grid"
218 severity failure;
219
220 CLK100_BUFG: bufg_unisim
221 port map (
222 I => I_CLK100,
223 O => CLK100_BUF
224 );
225
226 GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
227 generic map (
228 CLKIN_PERIOD => 10.0,
229 CLKIN_JITTER => 0.01,
230 STARTUP_WAIT => false,
231 CLK0_VCODIV => sys_conf_clksys_vcodivide,
232 CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
233 CLK0_OUTDIV => sys_conf_clksys_outdivide,
234 CLK0_GENTYPE => sys_conf_clksys_gentype,
235 CLK0_CDUWIDTH => 7,
236 CLK0_USECDIV => sys_conf_clksys_mhz,
237 CLK0_MSECDIV => 1000,
238 CLK1_VCODIV => sys_conf_clkser_vcodivide,
239 CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
240 CLK1_OUTDIV => sys_conf_clkser_outdivide,
241 CLK1_GENTYPE => sys_conf_clkser_gentype,
242 CLK1_CDUWIDTH => 7,
243 CLK1_USECDIV => sys_conf_clkser_mhz,
244 CLK1_MSECDIV => 1000,
245 CLK23_VCODIV => 1,
246 CLK23_VCOMUL => 16, -- vco 1600 MHz
247 CLK2_OUTDIV => 10, -- mig sys 160.0 MHz
248 CLK3_OUTDIV => 8, -- mig ref 200.0 MHz
249 CLK23_GENTYPE => "PLL")
250 port map (
251 CLKIN => CLK100_BUF,
252 CLK0 => CLK,
253 CE0_USEC => CE_USEC,
254 CE0_MSEC => CE_MSEC,
255 CLK1 => CLKS,
256 CE1_USEC => open,
257 CE1_MSEC => CES_MSEC,
258 CLK2 => CLKMIG,
259 CLK3 => CLKREF,
260 LOCKED => LOCKED
261 );
262
263 CDC_CLK_LOCKED : cdc_signal_s1_as
264 port map (
265 CLKO => CLK,
266 DI => LOCKED,
267 DO => LOCKED_CLK
268 );
269
270 GBL_RESET <= not LOCKED_CLK;
271
272 IOB_RS232 : bp_rs232_2line_iob -- serport iob ----------------------
273 port map (
274 CLK => CLKS,
275 RXD => RXD,
276 TXD => TXD,
277 I_RXD => I_RXD,
278 O_TXD => O_TXD
279 );
280
281 RLINK : rlink_sp2c -- rlink for serport -----------------
282 generic map (
283 BTOWIDTH => 9, -- 512 cycles, for slow mem iface
284 RTAWIDTH => 12,
285 SYSID => sysid_proj & sysid_board & sysid_vers ,
286 IFAWIDTH => 5, -- 32 word input fifo
287 OFAWIDTH => 5, -- 32 word output fifo
288 ENAPIN_RLMON => sbcntl_sbf_rlmon,
289 ENAPIN_RBMON => sbcntl_sbf_rbmon,
290 CDWIDTH => 12,
291 CDINIT => sys_conf_ser2rri_cdinit,
292 RBMON_AWIDTH => sys_conf_rbmon_awidth,
293 RBMON_RBADDR => rbaddr_rbmon)
294 port map (
295 CLK => CLK,
296 CE_USEC => CE_USEC,
297 CE_MSEC => CE_MSEC,
298 CE_INT => CE_MSEC,
299 RESET => RESET,
300 CLKS => CLKS,
301 CES_MSEC => CES_MSEC,
302 ENAXON => '1', -- XON statically enabled !
303 ESCFILL => '0',
304 RXSD => RXD,
305 TXSD => TXD,
306 CTS_N => '0',
307 RTS_N => open,
308 RB_MREQ => RB_MREQ,
309 RB_SRES => RB_SRES,
310 RB_LAM => RB_LAM,
311 RB_STAT => RB_STAT,
312 RL_MONI => open,
313 SER_MONI => SER_MONI
314 );
315
316 PERFEXT(0) <= MIG_MONI.rdrhit; -- ext_rdrhit
317 PERFEXT(1) <= MIG_MONI.wrrhit; -- ext_wrrhit
318 PERFEXT(2) <= MIG_MONI.wrflush; -- ext_wrflush
319 PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
320 PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
321 PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
322 PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
323 PERFEXT(7) <= CE_USEC; -- ext_usec
324
325 SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
326 port map (
327 CLK => CLK,
328 RESET => RESET,
329 RB_MREQ => RB_MREQ,
330 RB_SRES => RB_SRES_CPU,
331 RB_STAT => RB_STAT,
332 RB_LAM_CPU => RB_LAM(0),
333 GRESET => GRESET,
334 CRESET => CRESET,
335 BRESET => BRESET,
336 CP_STAT => CP_STAT,
337 EI_PRI => EI_PRI,
338 EI_VECT => EI_VECT,
339 EI_ACKM => EI_ACKM,
340 PERFEXT => PERFEXT,
341 IB_MREQ => IB_MREQ,
342 IB_SRES => IB_SRES_IBDR,
343 MEM_REQ => MEM_REQ,
344 MEM_WE => MEM_WE,
345 MEM_BUSY => MEM_BUSY,
346 MEM_ACK_R => MEM_ACK_R,
347 MEM_ADDR => MEM_ADDR,
348 MEM_BE => MEM_BE,
349 MEM_DI => MEM_DI,
350 MEM_DO => MEM_DO,
351 DM_STAT_EXP => DM_STAT_EXP
352 );
353
354
355 IBDR_SYS : ibdr_maxisys -- IO system -------------------------
356 port map (
357 CLK => CLK,
358 CE_USEC => CE_USEC,
359 CE_MSEC => CE_MSEC,
360 RESET => GRESET,
361 BRESET => BRESET,
362 ITIMER => DM_STAT_EXP.se_itimer,
363 IDEC => DM_STAT_EXP.se_idec,
364 CPUSUSP => CP_STAT.cpususp,
365 RB_LAM => RB_LAM(15 downto 1),
366 IB_MREQ => IB_MREQ,
367 IB_SRES => IB_SRES_IBDR,
368 EI_ACKM => EI_ACKM,
369 EI_PRI => EI_PRI,
370 EI_VECT => EI_VECT,
371 DISPREG => DISPREG
372 );
373
374 MEMCTL: sramif_mig_artys7 -- SRAM to MIG iface -----------------
375 port map (
376 CLK => CLK,
377 RESET => GBL_RESET,
378 REQ => MEM_REQ,
379 WE => MEM_WE,
380 BUSY => MEM_BUSY,
381 ACK_R => MEM_ACK_R,
382 ACK_W => open,
383 ACT_R => MEM_ACT_R,
384 ACT_W => MEM_ACT_W,
385 ADDR => MEM_ADDR,
386 BE => MEM_BE,
387 DI => MEM_DI,
388 DO => MEM_DO,
389 CLKMIG => CLKMIG,
390 CLKREF => CLKREF,
391 TEMP => XADC_TEMP,
392 MONI => MIG_MONI,
393 DDR3_DQ => DDR3_DQ,
394 DDR3_DQS_P => DDR3_DQS_P,
395 DDR3_DQS_N => DDR3_DQS_N,
396 DDR3_ADDR => DDR3_ADDR,
397 DDR3_BA => DDR3_BA,
398 DDR3_RAS_N => DDR3_RAS_N,
399 DDR3_CAS_N => DDR3_CAS_N,
400 DDR3_WE_N => DDR3_WE_N,
401 DDR3_RESET_N => DDR3_RESET_N,
402 DDR3_CK_P => DDR3_CK_P,
403 DDR3_CK_N => DDR3_CK_N,
404 DDR3_CKE => DDR3_CKE,
405 DDR3_CS_N => DDR3_CS_N,
406 DDR3_DM => DDR3_DM,
407 DDR3_ODT => DDR3_ODT
408 );
409
410 LED_IO : ioleds_sp1c -- hio leds from serport -------------
411 port map (
412 SER_MONI => SER_MONI,
413 IOLEDS => IOLEDS
414 );
415
416 ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
417
418 HIO70 : entity work.pdp11_hio70_artys7 -- hio from sys70 --------------------
419 port map (
420 CLK => CLK,
421 MODE => SWI,
424 CP_STAT => CP_STAT,
426 DISPREG => DISPREG,
427 IOLEDS => IOLEDS,
429 LED => LED,
430 RGB_R => RGB_R,
431 RGB_G => RGB_G,
432 RGB_B => RGB_B
433 );
434
435 HIO : bp_swibtnled
436 generic map (
437 SWIDTH => I_SWI'length,
438 BWIDTH => I_BTN'length,
439 LWIDTH => O_LED'length,
440 DEBOUNCE => sys_conf_hio_debounce)
441 port map (
442 CLK => CLK,
443 RESET => RESET,
444 CE_MSEC => CE_MSEC,
445 SWI => SWI,
446 BTN => BTN,
447 LED => LED,
448 I_SWI => I_SWI,
449 I_BTN => I_BTN,
450 O_LED => O_LED
451 );
452
453 HIORGB : rgbdrv_3x2mux
454 port map (
455 CLK => CLK,
456 RESET => RESET,
457 CE_USEC => CE_USEC,
458 DATR => RGB_R,
459 DATG => RGB_G,
460 DATB => RGB_B,
463 );
464
465 SMRB : sysmonx_rbus_base -- always instantiated, needed for mig
466 generic map ( -- use default INIT_ (Vccint=1.00)
467 CLK_MHZ => sys_conf_clksys_mhz,
468 RB_ADDR => rbaddr_sysmon)
469 port map (
470 CLK => CLK,
471 RESET => RESET,
472 RB_MREQ => RB_MREQ,
473 RB_SRES => RB_SRES_SYSMON,
474 ALM => open,
475 OT => open,
476 TEMP => XADC_TEMP
477 );
478
479 UARB : rbd_usracc
480 port map (
481 CLK => CLK,
482 RB_MREQ => RB_MREQ,
484 );
485
486 RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
487 port map (
488 RB_SRES_1 => RB_SRES_CPU,
489 RB_SRES_2 => RB_SRES_SYSMON,
490 RB_SRES_3 => RB_SRES_USRACC,
491 RB_SRES_OR => RB_SRES
492 );
493
494end syn;
DEBOUNCE boolean := true
SWIDTH positive := 4
out O_LED slv( LWIDTH- 1 downto 0)
out SWI slv( SWIDTH- 1 downto 0)
in I_BTN slv( BWIDTH- 1 downto 0)
LWIDTH positive := 4
in I_SWI slv( SWIDTH- 1 downto 0)
out BTN slv( BWIDTH- 1 downto 0)
in CLK slbit
BWIDTH positive := 4
in LED slv( LWIDTH- 1 downto 0)
in RESET slbit := '0'
in CE_MSEC slbit
in I std_ulogic
Definition: bufg_unisim.vhd:29
out O std_ulogic
Definition: bufg_unisim.vhd:27
Definition: iblib.vhd:33
in CP_STAT cp_stat_type
in DM_STAT_EXP dm_stat_exp_type
Definition: pdp11.vhd:123
in CLK slbit
Definition: rbd_usracc.vhd:40
in RB_MREQ rb_mreq_type
Definition: rbd_usracc.vhd:41
out RB_SRES rb_sres_type
Definition: rbd_usracc.vhd:43
Definition: rblib.vhd:32
in CE_USEC slbit
in CLK slbit
out O_RGBLED0 slv3
in RESET slbit := '0'
out O_RGBLED1 slv3
std_logic_vector( 13 downto 0) slv14
Definition: slvtypes.vhd:46
std_logic_vector( 19 downto 0) slv20
Definition: slvtypes.vhd:53
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 11 downto 0) slv12
Definition: slvtypes.vhd:44
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 8 downto 2) slv9_2
Definition: slvtypes.vhd:65
std_logic_vector( 0 downto 0) slv1
Definition: slvtypes.vhd:33
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
slbit := '0' CLKS
slv9_2 :=( others => '0') EI_VECT
slbit := '0' RESET
slbit := '0' GRESET
slv8 :=( others => '0') PERFEXT
slbit := '0' CLK100_BUF
slv16 := x"ffe8" rbaddr_rbmon
slbit := '0' EI_ACKM
slv12 :=( others => '0') XADC_TEMP
slv16 :=( others => '0') DISPREG
ib_mreq_type := ib_mreq_init IB_MREQ
slbit := '0' MEM_WE
bp_swibtnled hiohio
slv3 :=( others => '0') EI_PRI
slv2 :=( others => '0') RGB_G
slbit := '0' CLKMIG
slbit := '0' MEM_ACT_R
slv4 :=( others => '0') RB_STAT
sramif2migui_moni_type := sramif2migui_moni_init MIG_MONI
slv32 :=( others => '0') MEM_DI
rb_sres_type := rb_sres_init RB_SRES_SYSMON
slbit := '0' MEM_BUSY
rb_mreq_type := rb_mreq_init RB_MREQ
serport_moni_type := serport_moni_init SER_MONI
slbit := '0' MEM_REQ
slbit := '0' CE_USEC
slbit := '1' RXD
slbit := '0' LOCKED_CLK
slbit := '0' CE_MSEC
slbit := '0' MEM_ACT_W
slbit := '0' CES_MSEC
slv16 :=( others => '0') ABCLKDIV
slv32 :=( others => '0') MEM_DO
rlink_sp2c rlinkrlink
rb_sres_type := rb_sres_init RB_SRES
slv4 :=( others => '0') SWI
cp_stat_type := cp_stat_init CP_STAT
slv8 := x"00" sysid_vers
slbit := '0' CLK
rb_sres_type := rb_sres_init RB_SRES_CPU
slv16 := x"0201" sysid_proj
slv4 :=( others => '0') BTN
slbit := '0' BRESET
slv16 := x"fb00" rbaddr_sysmon
ib_sres_type := ib_sres_init IB_SRES_IBDR
slbit := '0' CLKREF
rb_sres_type := rb_sres_init RB_SRES_USRACC
slv16 :=( others => '0') RB_LAM
slbit := '0' GBL_RESET
slbit := '0' MEM_ACK_R
slbit := '0' CRESET
slv4 :=( others => '0') MEM_BE
slv2 :=( others => '0') RGB_B
slv8 := x"0a" sysid_board
dm_stat_exp_type := dm_stat_exp_init DM_STAT_EXP
slbit := '0' TXD
slbit := '0' LOCKED
slv2 :=( others => '0') RGB_R
slv4 :=( others => '0') IOLEDS
slv4 :=( others => '0') LED
slv20 :=( others => '0') MEM_ADDR
out DDR3_CK_P slv1
in I_SWI slv4
out DDR3_DM slv2
out O_TXD slbit
in I_RXD slbit
out DDR3_RESET_N slbit
out DDR3_BA slv3
inout DDR3_DQ slv16
in I_BTN slv4
out DDR3_WE_N slbit
out DDR3_CKE slv1
out DDR3_ADDR slv14
out DDR3_ODT slv1
out DDR3_CAS_N slbit
out DDR3_CK_N slv1
inout DDR3_DQS_P slv2
out O_RGBLED0 slv3
in I_CLK100 slbit
inout DDR3_DQS_N slv2
out DDR3_RAS_N slbit
out DDR3_CS_N slv1
out O_RGBLED1 slv3
out O_LED slv4
Definition: xlib.vhd:35