w11 - vhd 0.794
W11 CPU core and support modules
Loading...
Searching...
No Matches
sys_w11a_n3.vhd
Go to the documentation of this file.
1-- $Id: sys_w11a_n3.vhd 1325 2022-12-07 11:52:36Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2011-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_w11a_n3 - syn
7-- Description: w11a test design for nexys3
8--
9-- Dependencies: vlib/xlib/s6_cmt_sfs
10-- vlib/genlib/clkdivce
11-- bplib/bpgen/bp_rs232_2l4l_iob
12-- bplib/fx2rlink/rlink_sp1c_fx2
13-- w11a/pdp11_sys70
14-- ibus/ibdr_maxisys
15-- bplib/nxcramlib/nx_cram_memctl_as
16-- bplib/fx2rlink/ioleds_sp1c_fx2
17-- w11a/pdp11_hio70
18-- bplib/bpgen/sn_humanio_rbus
19-- vlib/rbus/rb_sres_or_2
20--
21-- Test bench: tb/tb_sys_w11a_n3
22--
23-- Target Devices: generic
24-- Tool versions: xst 13.1-14.7; ghdl 0.29-2.0.0
25--
26-- Synthesized (xst):
27-- Date Rev ise Target flop lutl lutm slic t peri
28-- 2022-12-06 1324 14.7 131013 xc6slx16-2 3227 6368 254 2182 ok: 95%
29-- 2019-05-19 1150 14.7 131013 xc6slx16-2 3167 6052 248 2130 ok: +dz11 93%
30-- 2019-05-01 1143 14.7 131013 xc6slx16-2 3062 5761 232 2057 ok: +m9312 90%
31-- 2019-04-27 1140 14.7 131013 xc6slx16-2 3053 5742 232 2050 ok: +dlbuf 89%
32-- 2019-04-24 1137 14.7 131013 xc6slx16-2 3049 5727 223 2045 ok: +pcbuf 89%
33-- 2019-03-17 1123 14.7 131013 xc6slx16-2 3059 5722 212 2041 ok: +lpbuf 89%
34-- 2019-03-02 1116 14.7 131013 xc6slx16-2 3048 5741 212 2030 ok: +ibtst 89%
35-- 2019-01-27 1108 14.7 131013 xc6slx16-2 2979 5542 201 2018 ok: -iist 88%
36-- 2018-10-13 1055 14.7 131013 xc6slx16-2 3057 5822 201 2064 ok: +dmpcnt 90%
37-- 2018-09-15 1045 14.7 131013 xc6slx16-2 2851 5453 177 1932 ok: +KW11P 84%
38-- 2017-03-30 888 14.7 131013 xc6slx16-2 2790 5352 177 1943 ok: +fx2dbg 85%
39-- 2017-03-04 858 14.7 131013 xc6slx16-2 2717 5273 177 1885 ok: +deuna 82%
40-- 2017-01-29 846 14.7 131013 xc6slx16-2 2680 5208 177 1860 ok: +int24 81%
41-- 2015-07-05 698 14.7 131013 xc6slx16-2 2500 4852 161 1782 ok: +dmhbpt 78%
42-- 2015-07-05 697 14.7 131013 xc6slx16-2 2428 4786 161 1756 ok: +dmcmon 77%
43-- 2015-06-27 695 14.7 131013 xc6slx16-2 2281 4638 161 1714 ok: +dmscnt 75%
44-- 2015-06-21 692 14.7 131013 xc6slx16-2 2192 4518 161 1584 ok: rhrp fixes
45-- 2015-06-04 686 14.7 131013 xc6slx16-2 2189 4492 161 1543 ok: +TM11 67%
46-- 2015-05-14 680 14.7 131013 xc6slx16-2 2120 4443 161 1546 ok: +ibmon 67%
47-- 2015-04-06 664 14.7 131013 xc6slx16-2 1991 4350 167 1489 ok: +RHRP 65%
48-- 2015-02-21 649 14.7 131013 xc6slx16-2 1819 3905 160 1380 ok: +RL11 61%
49-- 2014-12-22 619 14.7 131013 xc6slx16-2 1742 3767 150 1350 ok: +rbmon
50-- 2014-12-20 614 14.7 131013 xc6slx16-2 1640 3692 150 1297 ok: -RL11,rlv4
51-- 2014-06-08 561 14.7 131013 xc6slx16-2 1531 3500 142 1165 ok: +RL11
52-- 2014-05-29 556 14.7 131013 xc6slx16-2 1459 3342 128 1154 ok: 51%
53-- 2013-04-21 509 13.3 O76d xc6slx16-2 1516 3274 140 1184 ok: now + FX2 !
54-- 2011-12-18 440 13.1 O40d xc6slx16-2 1441 3161 96 1084 ok: LP+PC+DL+II
55-- 2011-11-20 430 13.1 O40d xc6slx16-2 1412 3206 84 1063 ok: LP+PC+DL+II
56--
57-- Revision History:
58-- Date Rev Version Comment
59-- 2018-10-13 1055 2.3 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
60-- 2017-04-30 888 2.2 use SWI(7:6) to allow fx2 debug via LEDs
61-- 2016-03-19 748 2.1.1 define rlink SYSID
62-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
63-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70
64-- 2015-04-24 668 1.8.3 added ibd_ibmon
65-- 2015-04-11 666 1.8.2 rearrange XON handling
66-- 2015-02-21 649 1.8.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux)
67-- 2015-02-15 647 1.8 drop bram and minisys options
68-- 2014-12-24 620 1.7.2 relocate ibus window and hio rbus address
69-- 2014-12-22 619 1.7.1 add rbus monitor rbd_rbmon
70-- 2014-08-28 588 1.7 use new rlink v4 iface generics and 4 bit STAT
71-- 2014-08-15 583 1.6 rb_mreq addr now 16 bit
72-- 2013-10-06 538 1.5 pll support, use clksys_vcodivide ect
73-- 2013-04-21 509 1.4 added fx2 (cuff) support
74-- 2011-12-18 440 1.0.4 use rlink_sp1c
75-- 2011-12-04 435 1.0.3 increase ATOWIDTH 6->7 (saw i/o timeouts on wblks)
76-- 2011-11-26 433 1.0.2 use nx_cram_(dummy|memctl_as) now
77-- 2011-11-23 432 1.0.1 fixup PPCM handling
78-- 2011-11-20 430 1.0 Initial version (derived from sys_w11a_n2)
79------------------------------------------------------------------------------
80--
81-- w11a test design for nexys3
82-- w11a + rlink + serport
83--
84-- Usage of Nexys 3 Switches, Buttons, LEDs:
85--
86-- SWI(7:6): select LED display mode
87-- 0x w11 sys70 LED display (further controlled by SWI(3))
88-- 10 FX2 debug: fx2 fifo states
89-- 11 FX2 debug: fx2 fsm states
90-- (5:4): select DSP
91-- 00 abclkdiv & abclkdiv_f
92-- 01 PC
93-- 10 DISPREG
94-- 11 DR emulation
95-- (3): select LED display
96-- 0 overall status
97-- 1 DR emulation
98-- (2) 0 -> int/ext RS242 port for rlink
99-- 1 -> use USB interface for rlink
100-- (1): 1 enable XON
101-- (0): 0 -> main board RS232 port
102-- 1 -> Pmod B/top RS232 port
103--
104-- LEDs if SWI(7) = 0 and SWI(3) = 1
105-- (7:0) DR emulation; shows R0(lower 8 bits) during wait like 11/45+70
106--
107-- LEDs if SWI(7) = 0 and SWI(3) = 0
108-- (7) MEM_ACT_W
109-- (6) MEM_ACT_R
110-- (5) cmdbusy (all rlink access, mostly rdma)
111-- (4:0) if cpugo=1 show cpu mode activity
112-- (4) kernel mode, pri>0
113-- (3) kernel mode, pri=0
114-- (2) kernel mode, wait
115-- (1) supervisor mode
116-- (0) user mode
117-- if cpugo=0 shows cpurust
118-- (4) '1'
119-- (3:0) cpurust code
120--
121-- LEDs if SWI(7) = 1
122-- (7) fifo_ep4
123-- (6) fifo_ep6
124-- (5) fsm_rx
125-- (4) fsm_tx
126-- LEDs if SWI(7) = 1 and SWI(6) = 0
127-- (3) flag_ep4_empty
128-- (2) flag_ep4_almost
129-- (1) flag_ep6_full
130-- (0) flag_ep6_almost
131-- LEDs if SWI(7) = 1 and SWI(6) = 1
132-- (3) fsm_idle
133-- (2) fsm_prep
134-- (1) fsm_disp
135-- (0) fsm_pipe
136--
137-- DP(3:0) shows IO activity
138-- if SWI(2)=0 (serport)
139-- (3): not SER_MONI.txok (shows tx back pressure)
140-- (2): SER_MONI.txact (shows tx activity)
141-- (1): not SER_MONI.rxok (shows rx back pressure)
142-- (0): SER_MONI.rxact (shows rx activity)
143-- if SWI(2)=1 (fx2-usb)
144-- (3): RB_SRES.busy (shows rbus back pressure)
145-- (2): RLB_TXBUSY (shows tx back pressure)
146-- (1): RLB_TXENA (shows tx activity)
147-- (0): RLB_RXVAL (shows rx activity)
148--
149
150library ieee;
151use ieee.std_logic_1164.all;
152use ieee.numeric_std.all;
153
154use work.slvtypes.all;
155use work.xlib.all;
156use work.genlib.all;
157use work.serportlib.all;
158use work.rblib.all;
159use work.rlinklib.all;
160use work.fx2lib.all;
161use work.fx2rlinklib.all;
162use work.bpgenlib.all;
163use work.bpgenrbuslib.all;
164use work.nxcramlib.all;
165use work.iblib.all;
166use work.ibdlib.all;
167use work.pdp11.all;
168use work.sys_conf.all;
169
170-- ----------------------------------------------------------------------------
171
172entity sys_w11a_n3 is -- top level
173 -- implements nexys3_fusp_cuff_aif
174 port (
175 I_CLK100 : in slbit; -- 100 MHz clock
176 I_RXD : in slbit; -- receive data (board view)
177 O_TXD : out slbit; -- transmit data (board view)
178 I_SWI : in slv8; -- n3 switches
179 I_BTN : in slv5; -- n3 buttons
180 O_LED : out slv8; -- n3 leds
181 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
182 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
183 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
184 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
185 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
186 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
187 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
188 O_MEM_CLK : out slbit; -- cram: clock
189 O_MEM_CRE : out slbit; -- cram: command register enable
190 I_MEM_WAIT : in slbit; -- cram: mem wait
191 O_MEM_ADDR : out slv23; -- cram: address lines
192 IO_MEM_DATA : inout slv16; -- cram: data lines
193 O_PPCM_CE_N : out slbit; -- ppcm: ...
194 O_PPCM_RST_N : out slbit; -- ppcm: ...
195 O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
196 I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
197 I_FUSP_RXD : in slbit; -- fusp: rs232 rx
198 O_FUSP_TXD : out slbit; -- fusp: rs232 tx
199 I_FX2_IFCLK : in slbit; -- fx2: interface clock
200 O_FX2_FIFO : out slv2; -- fx2: fifo address
201 I_FX2_FLAG : in slv4; -- fx2: fifo flags
202 O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
203 O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
204 O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
205 O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
206 IO_FX2_DATA : inout slv8 -- fx2: data lines
207 );
208end sys_w11a_n3;
209
210architecture syn of sys_w11a_n3 is
211
212 signal CLK : slbit := '0';
213
214 signal RESET : slbit := '0';
215 signal CE_USEC : slbit := '0';
216 signal CE_MSEC : slbit := '0';
217
218 signal RXD : slbit := '1';
219 signal TXD : slbit := '0';
220 signal RTS_N : slbit := '0';
221 signal CTS_N : slbit := '0';
222
223 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
224 signal RB_SRES : rb_sres_type := rb_sres_init;
225 signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
226 signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
227
228 signal RB_LAM : slv16 := (others=>'0');
229 signal RB_STAT : slv4 := (others=>'0');
230
231 signal RLB_MONI : rlb_moni_type := rlb_moni_init;
232 signal SER_MONI : serport_moni_type := serport_moni_init;
233 signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
234
235 signal GRESET : slbit := '0'; -- general reset (from rbus)
236 signal CRESET : slbit := '0'; -- cpu reset (from cp)
237 signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
238 signal PERFEXT : slv8 := (others=>'0');
239
240 signal EI_PRI : slv3 := (others=>'0');
241 signal EI_VECT : slv9_2 := (others=>'0');
242 signal EI_ACKM : slbit := '0';
243
244 signal CP_STAT : cp_stat_type := cp_stat_init;
245 signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
246
247 signal MEM_REQ : slbit := '0';
248 signal MEM_WE : slbit := '0';
249 signal MEM_BUSY : slbit := '0';
250 signal MEM_ACK_R : slbit := '0';
251 signal MEM_ACT_R : slbit := '0';
252 signal MEM_ACT_W : slbit := '0';
253 signal MEM_ADDR : slv20 := (others=>'0');
254 signal MEM_BE : slv4 := (others=>'0');
255 signal MEM_DI : slv32 := (others=>'0');
256 signal MEM_DO : slv32 := (others=>'0');
257
258 signal MEM_ADDR_EXT : slv22 := (others=>'0');
259
260 signal IB_MREQ : ib_mreq_type := ib_mreq_init;
261 signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
262
263 signal DISPREG : slv16 := (others=>'0');
264 signal ABCLKDIV : slv16 := (others=>'0');
265
266 signal LED70 : slv8 := (others=>'0');
267
268 signal SWI : slv8 := (others=>'0');
269 signal BTN : slv5 := (others=>'0');
270 signal LED : slv8 := (others=>'0');
271 signal DSP_DAT : slv16 := (others=>'0');
272 signal DSP_DP : slv4 := (others=>'0');
273
274 constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
275 constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
276
277 constant sysid_proj : slv16 := x"0201"; -- w11a
278 constant sysid_board : slv8 := x"03"; -- nexys3
279 constant sysid_vers : slv8 := x"00";
280
281begin
282
283 assert (sys_conf_clksys mod 1000000) = 0
284 report "assert sys_conf_clksys on MHz grid"
285 severity failure;
286
287 GEN_CLKSYS : s6_cmt_sfs -- clock generator -------------------
288 generic map (
289 VCO_DIVIDE => sys_conf_clksys_vcodivide,
290 VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
291 OUT_DIVIDE => sys_conf_clksys_outdivide,
292 CLKIN_PERIOD => 10.0,
293 CLKIN_JITTER => 0.01,
294 STARTUP_WAIT => false,
295 GEN_TYPE => sys_conf_clksys_gentype)
296 port map (
297 CLKIN => I_CLK100,
298 CLKFX => CLK,
299 LOCKED => open
300 );
301
302 CLKDIV : clkdivce -- usec/msec clock divider -----------
303 generic map (
304 CDUWIDTH => 7,
305 USECDIV => sys_conf_clksys_mhz,
306 MSECDIV => 1000)
307 port map (
308 CLK => CLK,
309 CE_USEC => CE_USEC,
310 CE_MSEC => CE_MSEC
311 );
312
313 IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ----------------
314 port map (
315 CLK => CLK,
316 RESET => '0',
317 SEL => SWI(0),
318 RXD => RXD,
319 TXD => TXD,
320 CTS_N => CTS_N,
321 RTS_N => RTS_N,
322 I_RXD0 => I_RXD,
323 O_TXD0 => O_TXD,
324 I_RXD1 => I_FUSP_RXD,
325 O_TXD1 => O_FUSP_TXD,
326 I_CTS1_N => I_FUSP_CTS_N,
327 O_RTS1_N => O_FUSP_RTS_N
328 );
329
330 RLINK : rlink_sp1c_fx2 -- rlink for serport + fx2 -----------
331 generic map (
332 BTOWIDTH => 7, -- 128 cycles access timeout
333 RTAWIDTH => 12,
334 SYSID => (others=>'0'),
335 IFAWIDTH => 5, -- 32 word input fifo
336 OFAWIDTH => 5, -- 32 word output fifo
337 PETOWIDTH => sys_conf_fx2_petowidth,
338 CCWIDTH => sys_conf_fx2_ccwidth,
339 ENAPIN_RLMON => sbcntl_sbf_rlmon,
340 ENAPIN_RBMON => sbcntl_sbf_rbmon,
341 CDWIDTH => 13,
342 CDINIT => sys_conf_ser2rri_cdinit,
343 RBMON_AWIDTH => sys_conf_rbmon_awidth,
344 RBMON_RBADDR => rbaddr_rbmon)
345 port map (
346 CLK => CLK,
347 CE_USEC => CE_USEC,
348 CE_MSEC => CE_MSEC,
349 CE_INT => CE_MSEC,
350 RESET => RESET,
351 ENAXON => SWI(1),
352 ENAFX2 => SWI(2),
353 RXSD => RXD,
354 TXSD => TXD,
355 CTS_N => CTS_N,
356 RTS_N => RTS_N,
357 RB_MREQ => RB_MREQ,
358 RB_SRES => RB_SRES,
359 RB_LAM => RB_LAM,
360 RB_STAT => RB_STAT,
361 RL_MONI => open,
362 RLB_MONI => RLB_MONI,
363 SER_MONI => SER_MONI,
364 FX2_MONI => FX2_MONI,
365 I_FX2_IFCLK => I_FX2_IFCLK,
366 O_FX2_FIFO => O_FX2_FIFO,
367 I_FX2_FLAG => I_FX2_FLAG,
368 O_FX2_SLRD_N => O_FX2_SLRD_N,
369 O_FX2_SLWR_N => O_FX2_SLWR_N,
370 O_FX2_SLOE_N => O_FX2_SLOE_N,
371 O_FX2_PKTEND_N => O_FX2_PKTEND_N,
372 IO_FX2_DATA => IO_FX2_DATA
373 );
374
375 PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
376 PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
377 PERFEXT(2) <= '0'; -- unused (ext_wrflush)
378 PERFEXT(3) <= RLB_MONI.rxval and not RLB_MONI.rxhold; -- ext_rlrxact
379 PERFEXT(4) <= RLB_MONI.rxhold; -- ext_rlrxback
380 PERFEXT(5) <= RLB_MONI.txena and not RLB_MONI.txbusy; -- ext_rltxact
381 PERFEXT(6) <= RLB_MONI.txbusy; -- ext_rltxback
382 PERFEXT(7) <= CE_USEC; -- ext_usec
383
384 SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
385 port map (
386 CLK => CLK,
387 RESET => RESET,
388 RB_MREQ => RB_MREQ,
389 RB_SRES => RB_SRES_CPU,
390 RB_STAT => RB_STAT,
391 RB_LAM_CPU => RB_LAM(0),
392 GRESET => GRESET,
393 CRESET => CRESET,
394 BRESET => BRESET,
395 CP_STAT => CP_STAT,
396 EI_PRI => EI_PRI,
397 EI_VECT => EI_VECT,
398 EI_ACKM => EI_ACKM,
399 PERFEXT => PERFEXT,
400 IB_MREQ => IB_MREQ,
401 IB_SRES => IB_SRES_IBDR,
402 MEM_REQ => MEM_REQ,
403 MEM_WE => MEM_WE,
404 MEM_BUSY => MEM_BUSY,
405 MEM_ACK_R => MEM_ACK_R,
406 MEM_ADDR => MEM_ADDR,
407 MEM_BE => MEM_BE,
408 MEM_DI => MEM_DI,
409 MEM_DO => MEM_DO,
410 DM_STAT_EXP => DM_STAT_EXP
411 );
412
413 IBDR_SYS : ibdr_maxisys -- IO system -------------------------
414 port map (
415 CLK => CLK,
416 CE_USEC => CE_USEC,
417 CE_MSEC => CE_MSEC,
418 RESET => GRESET,
419 BRESET => BRESET,
420 ITIMER => DM_STAT_EXP.se_itimer,
421 IDEC => DM_STAT_EXP.se_idec,
422 CPUSUSP => CP_STAT.cpususp,
423 RB_LAM => RB_LAM(15 downto 1),
424 IB_MREQ => IB_MREQ,
425 IB_SRES => IB_SRES_IBDR,
426 EI_ACKM => EI_ACKM,
427 EI_PRI => EI_PRI,
428 EI_VECT => EI_VECT,
429 DISPREG => DISPREG
430 );
431
432 MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
433
434 CRAMCTL: nx_cram_memctl_as -- memory controller -----------------
435 generic map (
436 READ0DELAY => sys_conf_memctl_read0delay,
437 READ1DELAY => sys_conf_memctl_read1delay,
438 WRITEDELAY => sys_conf_memctl_writedelay)
439 port map (
440 CLK => CLK,
441 RESET => GRESET,
442 REQ => MEM_REQ,
443 WE => MEM_WE,
444 BUSY => MEM_BUSY,
445 ACK_R => MEM_ACK_R,
446 ACK_W => open,
447 ACT_R => MEM_ACT_R,
448 ACT_W => MEM_ACT_W,
449 ADDR => MEM_ADDR_EXT,
450 BE => MEM_BE,
451 DI => MEM_DI,
452 DO => MEM_DO,
453 O_MEM_CE_N => O_MEM_CE_N,
454 O_MEM_BE_N => O_MEM_BE_N,
455 O_MEM_WE_N => O_MEM_WE_N,
456 O_MEM_OE_N => O_MEM_OE_N,
457 O_MEM_ADV_N => O_MEM_ADV_N,
458 O_MEM_CLK => O_MEM_CLK,
459 O_MEM_CRE => O_MEM_CRE,
460 I_MEM_WAIT => I_MEM_WAIT,
461 O_MEM_ADDR => O_MEM_ADDR,
462 IO_MEM_DATA => IO_MEM_DATA
463 );
464
465 O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
466 O_PPCM_RST_N <= '1'; --
467
468 LED_IO : ioleds_sp1c_fx2 -- hio leds from serport or fx2 ------
469 port map (
470 CLK => CLK,
471 CE_USEC => CE_USEC,
472 RESET => GRESET,
473 ENAFX2 => SWI(2),
474 RB_SRES => RB_SRES,
475 RLB_MONI => RLB_MONI,
476 SER_MONI => SER_MONI,
477 IOLEDS => DSP_DP
478 );
479
480 ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
481
482 HIO70 : pdp11_hio70 -- hio from sys70 --------------------
483 generic map (
484 LWIDTH => LED'length,
485 DCWIDTH => 2)
486 port map (
487 SEL_LED => SWI(3),
488 SEL_DSP => SWI(5 downto 4),
489 MEM_ACT_R => MEM_ACT_R,
490 MEM_ACT_W => MEM_ACT_W,
491 CP_STAT => CP_STAT,
492 DM_STAT_EXP => DM_STAT_EXP,
493 ABCLKDIV => ABCLKDIV,
494 DISPREG => DISPREG,
495 LED => LED70,
496 DSP_DAT => DSP_DAT
497 );
498
499 proc_fx2leds: process (SWI, LED70, FX2_MONI) -- hio LED handler ------------
500 variable iled : slv8 := (others=>'0');
501 begin
502
503 iled := (others=>'0');
504 if SWI(7) = '0' then
505 iled := LED70;
506 else
507 iled(7) := FX2_MONI.fifo_ep4;
508 iled(6) := FX2_MONI.fifo_ep6;
509 iled(5) := FX2_MONI.fsm_rx;
510 iled(4) := FX2_MONI.fsm_tx;
511 if SWI(6) = '0' then
512 iled(3) := FX2_MONI.flag_ep4_empty;
513 iled(2) := FX2_MONI.flag_ep4_almost;
514 iled(1) := FX2_MONI.flag_ep6_full;
515 iled(0) := FX2_MONI.flag_ep6_almost;
516 else
517 iled(3) := FX2_MONI.fsm_idle;
518 iled(2) := FX2_MONI.fsm_prep;
519 iled(1) := FX2_MONI.fsm_disp;
520 iled(0) := FX2_MONI.fsm_pipe;
521 end if;
522 end if;
523 LED <= iled;
524
525 end process proc_fx2leds;
526
527 HIO : sn_humanio_rbus -- hio manager -----------------------
528 generic map (
529 BWIDTH => 5,
530 DEBOUNCE => sys_conf_hio_debounce,
531 RB_ADDR => rbaddr_hio)
532 port map (
533 CLK => CLK,
534 RESET => RESET,
535 CE_MSEC => CE_MSEC,
536 RB_MREQ => RB_MREQ,
537 RB_SRES => RB_SRES_HIO,
538 SWI => SWI,
539 BTN => BTN,
540 LED => LED,
541 DSP_DAT => DSP_DAT,
542 DSP_DP => DSP_DP,
543 I_SWI => I_SWI,
544 I_BTN => I_BTN,
545 O_LED => O_LED,
546 O_ANO_N => O_ANO_N,
547 O_SEG_N => O_SEG_N
548 );
549
550 RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
551 port map (
552 RB_SRES_1 => RB_SRES_CPU,
553 RB_SRES_2 => RB_SRES_HIO,
554 RB_SRES_OR => RB_SRES
555 );
556
557end syn;
Definition: iblib.vhd:33
Definition: pdp11.vhd:123
Definition: rblib.vhd:32
std_logic_vector( 22 downto 0) slv23
Definition: slvtypes.vhd:56
std_logic_vector( 19 downto 0) slv20
Definition: slvtypes.vhd:53
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 8 downto 2) slv9_2
Definition: slvtypes.vhd:65
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic_vector( 21 downto 0) slv22
Definition: slvtypes.vhd:55
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
slv8 := x"03" sysid_board
slv8 :=( others => '0') LED70
slv9_2 :=( others => '0') EI_VECT
slv16 :=( others => '0') DSP_DAT
slbit := '0' RESET
slbit := '0' GRESET
slv8 :=( others => '0') PERFEXT
slv8 :=( others => '0') LED
slv16 := x"ffe8" rbaddr_rbmon
slv16 := x"fef0" rbaddr_hio
slbit := '0' EI_ACKM
slv16 :=( others => '0') DISPREG
fx2ctl_moni_type := fx2ctl_moni_init FX2_MONI
ib_mreq_type := ib_mreq_init IB_MREQ
slbit := '0' MEM_WE
sn_humanio_rbus hiohio
slv3 :=( others => '0') EI_PRI
slbit := '0' MEM_ACT_R
slv4 :=( others => '0') RB_STAT
slv8 :=( others => '0') SWI
slv32 :=( others => '0') MEM_DI
slbit := '0' MEM_BUSY
rb_mreq_type := rb_mreq_init RB_MREQ
serport_moni_type := serport_moni_init SER_MONI
slbit := '0' MEM_REQ
slbit := '0' CE_USEC
slbit := '1' RXD
pdp11_sys70 sys70sys70
slbit := '0' CE_MSEC
slbit := '0' MEM_ACT_W
slv16 :=( others => '0') ABCLKDIV
slv32 :=( others => '0') MEM_DO
rlink_sp1c_fx2 rlinkrlink
rb_sres_type := rb_sres_init RB_SRES
slv4 :=( others => '0') DSP_DP
cp_stat_type := cp_stat_init CP_STAT
slv8 := x"00" sysid_vers
slbit := '0' CLK
rb_sres_type := rb_sres_init RB_SRES_CPU
slv16 := x"0201" sysid_proj
slbit := '0' CTS_N
slv22 :=( others => '0') MEM_ADDR_EXT
slbit := '0' BRESET
ib_sres_type := ib_sres_init IB_SRES_IBDR
slv16 :=( others => '0') RB_LAM
rb_sres_type := rb_sres_init RB_SRES_HIO
slbit := '0' RTS_N
slbit := '0' MEM_ACK_R
slbit := '0' CRESET
slv4 :=( others => '0') MEM_BE
slv5 :=( others => '0') BTN
dm_stat_exp_type := dm_stat_exp_init DM_STAT_EXP
slbit := '0' TXD
rlb_moni_type := rlb_moni_init RLB_MONI
slv20 :=( others => '0') MEM_ADDR
inout IO_FX2_DATA slv8
out O_FUSP_TXD slbit
in I_FX2_IFCLK slbit
out O_TXD slbit
out O_FUSP_RTS_N slbit
in I_RXD slbit
out O_FX2_PKTEND_N slbit
out O_PPCM_CE_N slbit
out O_MEM_WE_N slbit
out O_LED slv8
in I_BTN slv5
in I_FUSP_CTS_N slbit
out O_FX2_SLWR_N slbit
out O_PPCM_RST_N slbit
out O_MEM_CE_N slbit
out O_SEG_N slv8
in I_FUSP_RXD slbit
in I_FX2_FLAG slv4
out O_FX2_FIFO slv2
in I_MEM_WAIT slbit
in I_CLK100 slbit
out O_MEM_OE_N slbit
out O_MEM_CLK slbit
out O_MEM_ADV_N slbit
out O_MEM_ADDR slv23
out O_MEM_BE_N slv2
inout IO_MEM_DATA slv16
out O_FX2_SLRD_N slbit
out O_FX2_SLOE_N slbit
out O_MEM_CRE slbit
in I_SWI slv8
out O_ANO_N slv4
Definition: xlib.vhd:35