63use ieee.std_logic_1164.
all;
64use ieee.numeric_std.
all;
114 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
115 signal RB_SRES : rb_sres_type := rb_sres_init;
124 signal SER_MONI : serport_moni_type := serport_moni_init;
134 signal CP_STAT : cp_stat_type := cp_stat_init;
165 signal IB_MREQ : ib_mreq_type := ib_mreq_init;
189 assert (sys_conf_clksys mod 1000000) = 0
190 report "assert sys_conf_clksys on MHz grid"
193 GEN_CLKALL :
s7_cmt_1ce1ce -- clock generator system ------------
195 CLKIN_PERIOD =>
83.3,
196 CLKIN_JITTER =>
0.01,
197 STARTUP_WAIT => false,
198 CLK0_VCODIV => sys_conf_clksys_vcodivide,
199 CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
200 CLK0_OUTDIV => sys_conf_clksys_outdivide,
201 CLK0_GENTYPE => sys_conf_clksys_gentype,
203 CLK0_USECDIV => sys_conf_clksys_mhz,
204 CLK0_MSECDIV =>
1000,
205 CLK1_VCODIV => sys_conf_clkser_vcodivide,
206 CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
207 CLK1_OUTDIV => sys_conf_clkser_outdivide,
208 CLK1_GENTYPE => sys_conf_clkser_gentype,
210 CLK1_USECDIV => sys_conf_clkser_mhz,
211 CLK1_MSECDIV =>
1000)
236 SYSID => sysid_proj & sysid_board & sysid_vers ,
239 ENAPIN_RLMON => sbcntl_sbf_rlmon,
240 ENAPIN_RBMON => sbcntl_sbf_rbmon,
242 CDINIT => sys_conf_ser2rri_cdinit,
243 RBMON_AWIDTH => sys_conf_rbmon_awidth,
276 SYS70 :
pdp11_sys70 --
1 cpu system ----------------------
306 IBDR_SYS :
ibdr_maxisys -- IO system -------------------------
313 ITIMER => DM_STAT_EXP.se_itimer,
314 IDEC => DM_STAT_EXP.se_idec,
315 CPUSUSP => CP_STAT.cpususp,
316 RB_LAM =>
RB_LAM(15 downto 1),
326 proc_a17reg:
process (
CLK)
329 if rising_edge(CLK) then
339 end process proc_a17reg;
367 end process proc_a17mux;
393 MAWIDTH => sys_conf_memctl_mawidth,
394 NBLOCK => sys_conf_memctl_nblock
)
411 LED_IO :
ioleds_sp1c -- hio leds from serport -------------
421 LWIDTH => ELED'length,
425 SEL_DSP =>
ESWI(5 downto 4),
454 SMRB : if sys_conf_rbd_sysmon generate
457 CLK_MHZ => sys_conf_clksys_mhz,
477 RB_SRES_OR :
rb_sres_or_4 -- rbus
or ---------------------------
487 generic map (
DWIDTH => O_LED'length
)
out PAD slv( DWIDTH- 1 downto 0)
in DO slv( DWIDTH- 1 downto 0)
std_logic_vector( 19 downto 0) slv20
std_logic_vector( 18 downto 0) slv19
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 4 downto 0) slv5
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 8 downto 2) slv9_2
std_logic_vector( 31 downto 0) slv32
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2
slbit := '0' MEM_ACK_R_SRAM
slv9_2 :=( others => '0') EI_VECT
slv8 :=( others => '0') PERFEXT
slbit := '0' MEM_ACT_R_BRAM
slv16 := x"ffe8" rbaddr_rbmon
slv16 := x"fef0" rbaddr_hio
slv2 :=( others => '0') LED
slv16 :=( others => '0') DISPREG
slbit := '0' MEM_ACT_W_SRAM
ib_mreq_type := ib_mreq_init IB_MREQ
slv8 := x"09" sysid_board
slv8 :=( others => '0') EDSP_DP
slv3 :=( others => '0') EI_PRI
slv4 :=( others => '0') RB_STAT
slbit := '0' MEM_REQ_BRAM
slbit := '0' MEM_ACT_R_SRAM
slv32 :=( others => '0') MEM_DI
rb_sres_type := rb_sres_init RB_SRES_SYSMON
rb_mreq_type := rb_mreq_init RB_MREQ
serport_moni_type := serport_moni_init SER_MONI
slbit := '0' MEM_BUSY_SRAM
slv5 :=( others => '0') EBTN
slbit := '0' MEM_BUSY_BRAM
slv16 :=( others => '0') ABCLKDIV
slv32 :=( others => '0') MEM_DO
slbit := '0' MEM_ACK_R_BRAM
rb_sres_type := rb_sres_init RB_SRES
cp_stat_type := cp_stat_init CP_STAT
slv16 :=( others => '0') ESWI
slv32 :=( others => '0') MEM_DO_BRAM
slv32 :=( others => '0') MEM_DO_SRAM
rb_sres_type := rb_sres_init RB_SRES_CPU
slv16 := x"0201" sysid_proj
slv32 :=( others => '0') EDSP_DAT
slv16 := x"fb00" rbaddr_sysmon
ib_sres_type := ib_sres_init IB_SRES_IBDR
rb_sres_type := rb_sres_init RB_SRES_USRACC
slv16 :=( others => '0') RB_LAM
rb_sres_type := rb_sres_init RB_SRES_HIO
slv20 :=( others => '0') MEM_ADDR_BRAM
slv4 :=( others => '0') MEM_BE
dm_stat_exp_type := dm_stat_exp_init DM_STAT_EXP
slbit := '0' MEM_ACT_W_BRAM
slv16 :=( others => '0') ELED
slbit := '0' MEM_REQ_SRAM
slv20 :=( others => '0') MEM_ADDR