w11 - vhd 0.794
W11 CPU core and support modules
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sys_w11a_c7.vhd
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1-- $Id: sys_w11a_c7.vhd 1349 2023-01-11 14:52:42Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2017-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_w11a_c7 - syn
7-- Description: w11a test design for Cmod A7
8--
9-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce
10-- bplib/bpgen/bp_rs232_2line_iob
11-- vlib/rlink/rlink_sp2c
12-- w11a/pdp11_sys70
13-- ibus/ibdr_maxisys
14-- bplib/cmoda7/c7_cram_memctl
15-- w11a/pdp11_bram_memctl
16-- bplib/fx2rlink/ioleds_sp1c
17-- w11a/pdp11_hio70
18-- bplib/bpgen/sn_humanio_emu_rbus
19-- bplib/sysmon/sysmonx_rbus_base
20-- vlib/rbus/rbd_usracc
21-- vlib/rbus/rb_sres_or_4
22-- vlib/xlib/iob_reg_o_gen
23--
24-- Test bench: tb/tb_sys_w11a_c7
25--
26-- Target Devices: generic
27-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0
28--
29-- Synthesized:
30-- Date Rev viv Target flop lutl lutm bram slic
31-- 2023-01-11 1349 2022.1 xc7a35t-1 3451 6019 279 50.0 2006
32-- 2023-01-02 1342 2022.1 xc7a35t-1 3434 6005 279 50.0 1969
33-- 2022-12-31 1340 2022.1 xc7a35t-1 3450 6018 279 50.0 1986
34-- 2022-12-27 1339 2022.1 xc7a35t-1 3454 6026 279 50.0 2013
35-- 2022-12-06 1324 2022.1 xc7a35t-1 3447 5998 278 50.0 1992
36-- 2022-07-05 1247 2022.1 xc7a35t-1 3411 6189 279 50.0 2021
37-- 2019-05-19 1150 2017.2 xc7a35t-1 3369 6994 285 50.0 2099 +dz11
38-- 2019-04-27 1140 2017.2 xc7a35t-1 3243 6618 260 50.0 2009 +ibtst
39-- 2019-03-02 1116 2017.2 xc7a35t-1 3156 6332 198 50.0 1918 +ibtst
40-- 2019-02-02 1108 2018.3 xc7a35t-1 3112 6457 182 50.0 1936
41-- 2019-02-02 1108 2017.2 xc7a35t-1 3107 6216 182 50.0 1884
42-- 2018-10-13 1055 2017.2 xc7a35t-1 3107 6215 182 50.0 1889 +dmpcnt
43-- 2018-09-15 1045 2017.2 xc7a35t-1 2883 5891 150 50.0 1826 +KW11P
44-- 2017-06-27 918 2017.1 xc7a35t-1 2823 5827 150 50.0 1814 16kB cache
45-- 2017-06-25 916 2017.1 xc7a35t-1 2823 5796 150 47.5 1744 +BRAM
46-- 2017-06-24 914 2017.1 xc7a35t-1 2708 5668 150 26.0 1787
47--
48-- Revision History:
49-- Date Rev Version Comment
50-- 2018-12-16 1086 1.3 use s7_cmt_1ce1ce
51-- 2018-10-13 1055 1.2 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
52-- 2017-06-27 918 1.1.1 use 16 kB cache (all BRAM's used up)
53-- 2017-06-25 916 1.1 add bram_memctl for 672 kB total memory
54-- 2017-06-24 914 1.0 Initial version (derived from sys_w11a_n4)
55------------------------------------------------------------------------------
56--
57-- w11a test design for Cmod A7 (using SRAM+BRAM as memory)
58-- w11a + rlink + serport
59--
60--
61
62library ieee;
63use ieee.std_logic_1164.all;
64use ieee.numeric_std.all;
65
66use work.slvtypes.all;
67use work.xlib.all;
68use work.serportlib.all;
69use work.rblib.all;
70use work.rbdlib.all;
71use work.rlinklib.all;
72use work.bpgenlib.all;
73use work.bpgenrbuslib.all;
74use work.sysmonrbuslib.all;
75use work.cmoda7lib.all;
76use work.iblib.all;
77use work.ibdlib.all;
78use work.pdp11.all;
79use work.sys_conf.all;
80
81-- ----------------------------------------------------------------------------
82
83entity sys_w11a_c7 is -- top level
84 -- implements cmoda7_sram_aif
85 port (
86 I_CLK12 : in slbit; -- 12 MHz clock
87 I_RXD : in slbit; -- receive data (board view)
88 O_TXD : out slbit; -- transmit data (board view)
89 I_BTN : in slv2; -- c7 buttons
90 O_LED : out slv2; -- c7 leds
91 O_RGBLED0_N : out slv3; -- c7 rgb-led 0
92 O_MEM_CE_N : out slbit; -- sram: chip enable (act.low)
93 O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
94 O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
95 O_MEM_ADDR : out slv19; -- sram: address lines
96 IO_MEM_DATA : inout slv8 -- sram: data lines
97 );
98end sys_w11a_c7;
99
100architecture syn of sys_w11a_c7 is
101
102 signal CLK : slbit := '0';
103
104 signal RESET : slbit := '0';
105 signal CE_USEC : slbit := '0';
106 signal CE_MSEC : slbit := '0';
107
108 signal CLKS : slbit := '0';
109 signal CES_MSEC : slbit := '0';
110
111 signal RXD : slbit := '1';
112 signal TXD : slbit := '0';
113
114 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
115 signal RB_SRES : rb_sres_type := rb_sres_init;
116 signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
117 signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
118 signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
119 signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
120
121 signal RB_LAM : slv16 := (others=>'0');
122 signal RB_STAT : slv4 := (others=>'0');
123
124 signal SER_MONI : serport_moni_type := serport_moni_init;
125
126 signal GRESET : slbit := '0'; -- general reset (from rbus)
127 signal CRESET : slbit := '0'; -- cpu reset (from cp)
128 signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
129 signal PERFEXT : slv8 := (others=>'0');
130
131 signal EI_PRI : slv3 := (others=>'0');
132 signal EI_VECT : slv9_2 := (others=>'0');
133 signal EI_ACKM : slbit := '0';
134 signal CP_STAT : cp_stat_type := cp_stat_init;
135 signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
136
137 signal MEM_REQ : slbit := '0';
138 signal MEM_WE : slbit := '0';
139 signal MEM_BUSY : slbit := '0';
140 signal MEM_ACK_R : slbit := '0';
141 signal MEM_ACT_R : slbit := '0';
142 signal MEM_ACT_W : slbit := '0';
143 signal MEM_ADDR : slv20 := (others=>'0');
144 signal MEM_BE : slv4 := (others=>'0');
145 signal MEM_DI : slv32 := (others=>'0');
146 signal MEM_DO : slv32 := (others=>'0');
147
148 signal MEM_REQ_SRAM : slbit := '0';
149 signal MEM_BUSY_SRAM : slbit := '0';
150 signal MEM_ACK_R_SRAM : slbit := '0';
151 signal MEM_ACT_R_SRAM : slbit := '0';
152 signal MEM_ACT_W_SRAM : slbit := '0';
153 signal MEM_DO_SRAM : slv32 := (others=>'0');
154
155 signal MEM_REQ_BRAM : slbit := '0';
156 signal MEM_BUSY_BRAM : slbit := '0';
157 signal MEM_ACK_R_BRAM : slbit := '0';
158 signal MEM_ACT_R_BRAM : slbit := '0';
159 signal MEM_ACT_W_BRAM : slbit := '0';
160 signal MEM_ADDR_BRAM : slv20 := (others=>'0');
161 signal MEM_DO_BRAM : slv32 := (others=>'0');
162
163 signal R_MEM_A17 : slbit := '0';
164
165 signal IB_MREQ : ib_mreq_type := ib_mreq_init;
166 signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
167
168 signal DISPREG : slv16 := (others=>'0');
169 signal ABCLKDIV : slv16 := (others=>'0');
170
171 signal ESWI : slv16 := (others=>'0');
172 signal EBTN : slv5 := (others=>'0');
173 signal ELED : slv16 := (others=>'0');
174 signal EDSP_DAT : slv32 := (others=>'0');
175 signal EDSP_DP : slv8 := (others=>'0');
176
177 signal LED : slv2 := (others=>'0');
178
179 constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
180 constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
181 constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
182
183 constant sysid_proj : slv16 := x"0201"; -- w11a
184 constant sysid_board : slv8 := x"09"; -- cmoda7
185 constant sysid_vers : slv8 := x"00";
186
187begin
188
189 assert (sys_conf_clksys mod 1000000) = 0
190 report "assert sys_conf_clksys on MHz grid"
191 severity failure;
192
193 GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
194 generic map (
195 CLKIN_PERIOD => 83.3,
196 CLKIN_JITTER => 0.01,
197 STARTUP_WAIT => false,
198 CLK0_VCODIV => sys_conf_clksys_vcodivide,
199 CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
200 CLK0_OUTDIV => sys_conf_clksys_outdivide,
201 CLK0_GENTYPE => sys_conf_clksys_gentype,
202 CLK0_CDUWIDTH => 7,
203 CLK0_USECDIV => sys_conf_clksys_mhz,
204 CLK0_MSECDIV => 1000,
205 CLK1_VCODIV => sys_conf_clkser_vcodivide,
206 CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
207 CLK1_OUTDIV => sys_conf_clkser_outdivide,
208 CLK1_GENTYPE => sys_conf_clkser_gentype,
209 CLK1_CDUWIDTH => 7,
210 CLK1_USECDIV => sys_conf_clkser_mhz,
211 CLK1_MSECDIV => 1000)
212 port map (
213 CLKIN => I_CLK12,
214 CLK0 => CLK,
215 CE0_USEC => CE_USEC,
216 CE0_MSEC => CE_MSEC,
217 CLK1 => CLKS,
218 CE1_USEC => open,
219 CE1_MSEC => CES_MSEC,
220 LOCKED => open
221 );
222
223 IOB_RS232 : bp_rs232_2line_iob -- serport iob ----------------------
224 port map (
225 CLK => CLKS,
226 RXD => RXD,
227 TXD => TXD,
228 I_RXD => I_RXD,
229 O_TXD => O_TXD
230 );
231
232 RLINK : rlink_sp2c -- rlink for serport -----------------
233 generic map (
234 BTOWIDTH => 7, -- 128 cycles access timeout
235 RTAWIDTH => 12,
236 SYSID => sysid_proj & sysid_board & sysid_vers ,
237 IFAWIDTH => 5, -- 32 word input fifo
238 OFAWIDTH => 5, -- 32 word output fifo
239 ENAPIN_RLMON => sbcntl_sbf_rlmon,
240 ENAPIN_RBMON => sbcntl_sbf_rbmon,
241 CDWIDTH => 12,
242 CDINIT => sys_conf_ser2rri_cdinit,
243 RBMON_AWIDTH => sys_conf_rbmon_awidth,
244 RBMON_RBADDR => rbaddr_rbmon)
245 port map (
246 CLK => CLK,
247 CE_USEC => CE_USEC,
248 CE_MSEC => CE_MSEC,
249 CE_INT => CE_MSEC,
250 RESET => RESET,
251 CLKS => CLKS,
252 CES_MSEC => CES_MSEC,
253 ENAXON => '1', -- XON statically enabled !
254 ESCFILL => '0',
255 RXSD => RXD,
256 TXSD => TXD,
257 CTS_N => '0',
258 RTS_N => open,
259 RB_MREQ => RB_MREQ,
260 RB_SRES => RB_SRES,
261 RB_LAM => RB_LAM,
262 RB_STAT => RB_STAT,
263 RL_MONI => open,
264 SER_MONI => SER_MONI
265 );
266
267 PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
268 PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
269 PERFEXT(2) <= '0'; -- unused (ext_wrflush)
270 PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
271 PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
272 PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
273 PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
274 PERFEXT(7) <= CE_USEC; -- ext_usec
275
276 SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
277 port map (
278 CLK => CLK,
279 RESET => RESET,
280 RB_MREQ => RB_MREQ,
281 RB_SRES => RB_SRES_CPU,
282 RB_STAT => RB_STAT,
283 RB_LAM_CPU => RB_LAM(0),
284 GRESET => GRESET,
285 CRESET => CRESET,
286 BRESET => BRESET,
287 CP_STAT => CP_STAT,
288 EI_PRI => EI_PRI,
289 EI_VECT => EI_VECT,
290 EI_ACKM => EI_ACKM,
291 PERFEXT => PERFEXT,
292 IB_MREQ => IB_MREQ,
293 IB_SRES => IB_SRES_IBDR,
294 MEM_REQ => MEM_REQ,
295 MEM_WE => MEM_WE,
296 MEM_BUSY => MEM_BUSY,
297 MEM_ACK_R => MEM_ACK_R,
298 MEM_ADDR => MEM_ADDR,
299 MEM_BE => MEM_BE,
300 MEM_DI => MEM_DI,
301 MEM_DO => MEM_DO,
302 DM_STAT_EXP => DM_STAT_EXP
303 );
304
305
306 IBDR_SYS : ibdr_maxisys -- IO system -------------------------
307 port map (
308 CLK => CLK,
309 CE_USEC => CE_USEC,
310 CE_MSEC => CE_MSEC,
311 RESET => GRESET,
312 BRESET => BRESET,
313 ITIMER => DM_STAT_EXP.se_itimer,
314 IDEC => DM_STAT_EXP.se_idec,
315 CPUSUSP => CP_STAT.cpususp,
316 RB_LAM => RB_LAM(15 downto 1),
317 IB_MREQ => IB_MREQ,
318 IB_SRES => IB_SRES_IBDR,
319 EI_ACKM => EI_ACKM,
320 EI_PRI => EI_PRI,
321 EI_VECT => EI_VECT,
322 DISPREG => DISPREG
323 );
324
325 -- logic to distribute/collect request/response to SRAM/BRAM
326 proc_a17reg: process (CLK)
327 begin
328
329 if rising_edge(CLK) then
330 if GRESET = '1' then
331 R_MEM_A17 <= '0';
332 else
333 if MEM_REQ = '1' then
334 R_MEM_A17 <= MEM_ADDR(17);
335 end if;
336 end if;
337 end if;
338
339 end process proc_a17reg;
340
341 proc_a17mux: process (R_MEM_A17, MEM_REQ, MEM_ADDR,
347 begin
348
349 MEM_REQ_SRAM <= MEM_REQ and not MEM_ADDR(17);
350 MEM_REQ_BRAM <= MEM_REQ and MEM_ADDR(17);
351 MEM_ADDR_BRAM <= "000" & MEM_ADDR(16 downto 0);
352
353 if R_MEM_A17 = '0' then
359 else
365 end if;
366
367 end process proc_a17mux;
368
369 SRAM_CTL : c7_sram_memctl -- SRAM memory controller ------------
370 port map (
371 CLK => CLK,
372 RESET => GRESET,
373 REQ => MEM_REQ_SRAM,
374 WE => MEM_WE,
375 BUSY => MEM_BUSY_SRAM,
376 ACK_R => MEM_ACK_R_SRAM,
377 ACK_W => open,
378 ACT_R => MEM_ACT_R_SRAM,
379 ACT_W => MEM_ACT_W_SRAM,
380 ADDR => MEM_ADDR(16 downto 0),
381 BE => MEM_BE,
382 DI => MEM_DI,
383 DO => MEM_DO_SRAM,
384 O_MEM_CE_N => O_MEM_CE_N,
385 O_MEM_WE_N => O_MEM_WE_N,
386 O_MEM_OE_N => O_MEM_OE_N,
387 O_MEM_ADDR => O_MEM_ADDR,
388 IO_MEM_DATA => IO_MEM_DATA
389 );
390
391 BRAM_CTL: pdp11_bram_memctl -- BRAM memory controller ------------
392 generic map (
393 MAWIDTH => sys_conf_memctl_mawidth,
394 NBLOCK => sys_conf_memctl_nblock)
395 port map (
396 CLK => CLK,
397 RESET => GRESET,
398 REQ => MEM_REQ_BRAM,
399 WE => MEM_WE,
400 BUSY => MEM_BUSY_BRAM,
401 ACK_R => MEM_ACK_R_BRAM,
402 ACK_W => open,
403 ACT_R => MEM_ACT_R_BRAM,
404 ACT_W => MEM_ACT_W_BRAM,
405 ADDR => MEM_ADDR_BRAM,
406 BE => MEM_BE,
407 DI => MEM_DI,
408 DO => MEM_DO_BRAM
409 );
410
411 LED_IO : ioleds_sp1c -- hio leds from serport -------------
412 port map (
413 SER_MONI => SER_MONI,
414 IOLEDS => EDSP_DP(3 downto 0)
415 );
416
417 ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
418
419 HIO70 : pdp11_hio70 -- hio from sys70 --------------------
420 generic map (
421 LWIDTH => ELED'length,
422 DCWIDTH => 3)
423 port map (
424 SEL_LED => ESWI(3),
425 SEL_DSP => ESWI(5 downto 4),
426 MEM_ACT_R => MEM_ACT_R,
427 MEM_ACT_W => MEM_ACT_W,
428 CP_STAT => CP_STAT,
429 DM_STAT_EXP => DM_STAT_EXP,
430 ABCLKDIV => ABCLKDIV,
431 DISPREG => DISPREG,
432 LED => ELED,
433 DSP_DAT => EDSP_DAT
434 );
435
436 EHIO : sn_humanio_emu_rbus -- emulated hio ----------------------
437 generic map (
438 SWIDTH => 16,
439 BWIDTH => 5,
440 LWIDTH => 16,
441 DCWIDTH => 3)
442 port map (
443 CLK => CLK,
444 RESET => '0',
445 RB_MREQ => RB_MREQ,
446 RB_SRES => RB_SRES_HIO,
447 SWI => ESWI,
448 BTN => EBTN,
449 LED => ELED,
450 DSP_DAT => EDSP_DAT,
451 DSP_DP => EDSP_DP
452 );
453
454 SMRB : if sys_conf_rbd_sysmon generate
456 generic map ( -- use default INIT_ (LP: Vccint=1.00)
457 CLK_MHZ => sys_conf_clksys_mhz,
459 port map (
460 CLK => CLK,
461 RESET => RESET,
462 RB_MREQ => RB_MREQ,
464 ALM => open,
465 OT => open,
466 TEMP => open
467 );
468 end generate SMRB;
469
470 UARB : rbd_usracc
471 port map (
472 CLK => CLK,
473 RB_MREQ => RB_MREQ,
475 );
476
477 RB_SRES_OR : rb_sres_or_4 -- rbus or ---------------------------
478 port map (
479 RB_SRES_1 => RB_SRES_CPU,
480 RB_SRES_2 => RB_SRES_HIO,
481 RB_SRES_3 => RB_SRES_SYSMON,
482 RB_SRES_4 => RB_SRES_USRACC,
483 RB_SRES_OR => RB_SRES
484 );
485
486 IOB_LED : iob_reg_o_gen
487 generic map (DWIDTH => O_LED'length)
488 port map (CLK => CLK, CE => '1', DO => LED, PAD => O_LED);
489
490 LED(1) <= SER_MONI.txact;
491 LED(0) <= SER_MONI.rxact;
492
493 -- setup unused outputs in cmoda7
494 O_RGBLED0_N <= (others=>'1');
495
496end syn;
Definition: iblib.vhd:33
in CE slbit := '1'
out PAD slv( DWIDTH- 1 downto 0)
in CLK slbit
in DO slv( DWIDTH- 1 downto 0)
DWIDTH positive := 16
Definition: pdp11.vhd:123
in CLK slbit
Definition: rbd_usracc.vhd:40
in RB_MREQ rb_mreq_type
Definition: rbd_usracc.vhd:41
out RB_SRES rb_sres_type
Definition: rbd_usracc.vhd:43
Definition: rblib.vhd:32
std_logic_vector( 19 downto 0) slv20
Definition: slvtypes.vhd:53
std_logic_vector( 18 downto 0) slv19
Definition: slvtypes.vhd:52
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 8 downto 2) slv9_2
Definition: slvtypes.vhd:65
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
slbit := '0' MEM_ACK_R_SRAM
slbit := '0' CLKS
slv9_2 :=( others => '0') EI_VECT
slbit := '0' RESET
slbit := '0' GRESET
slv8 :=( others => '0') PERFEXT
slbit := '0' MEM_ACT_R_BRAM
slv16 := x"ffe8" rbaddr_rbmon
slv16 := x"fef0" rbaddr_hio
slbit := '0' EI_ACKM
slv2 :=( others => '0') LED
slv16 :=( others => '0') DISPREG
slbit := '0' R_MEM_A17
slbit := '0' MEM_ACT_W_SRAM
ib_mreq_type := ib_mreq_init IB_MREQ
slv8 := x"09" sysid_board
slv8 :=( others => '0') EDSP_DP
slbit := '0' MEM_WE
slv3 :=( others => '0') EI_PRI
slbit := '0' MEM_ACT_R
slv4 :=( others => '0') RB_STAT
slbit := '0' MEM_REQ_BRAM
slbit := '0' MEM_ACT_R_SRAM
slv32 :=( others => '0') MEM_DI
rb_sres_type := rb_sres_init RB_SRES_SYSMON
slbit := '0' MEM_BUSY
rb_mreq_type := rb_mreq_init RB_MREQ
serport_moni_type := serport_moni_init SER_MONI
slbit := '0' MEM_BUSY_SRAM
slbit := '0' MEM_REQ
slbit := '0' CE_USEC
slv5 :=( others => '0') EBTN
slbit := '1' RXD
pdp11_sys70 sys70sys70
slbit := '0' CE_MSEC
slbit := '0' MEM_ACT_W
slbit := '0' MEM_BUSY_BRAM
slbit := '0' CES_MSEC
slv16 :=( others => '0') ABCLKDIV
slv32 :=( others => '0') MEM_DO
rlink_sp2c rlinkrlink
slbit := '0' MEM_ACK_R_BRAM
rb_sres_type := rb_sres_init RB_SRES
cp_stat_type := cp_stat_init CP_STAT
slv16 :=( others => '0') ESWI
slv32 :=( others => '0') MEM_DO_BRAM
slv32 :=( others => '0') MEM_DO_SRAM
slv8 := x"00" sysid_vers
slbit := '0' CLK
rb_sres_type := rb_sres_init RB_SRES_CPU
slv16 := x"0201" sysid_proj
slv32 :=( others => '0') EDSP_DAT
slbit := '0' BRESET
slv16 := x"fb00" rbaddr_sysmon
ib_sres_type := ib_sres_init IB_SRES_IBDR
rb_sres_type := rb_sres_init RB_SRES_USRACC
slv16 :=( others => '0') RB_LAM
rb_sres_type := rb_sres_init RB_SRES_HIO
slbit := '0' MEM_ACK_R
slv20 :=( others => '0') MEM_ADDR_BRAM
slbit := '0' CRESET
slv4 :=( others => '0') MEM_BE
dm_stat_exp_type := dm_stat_exp_init DM_STAT_EXP
slbit := '0' TXD
slbit := '0' MEM_ACT_W_BRAM
slv16 :=( others => '0') ELED
slbit := '0' MEM_REQ_SRAM
slv20 :=( others => '0') MEM_ADDR
in I_BTN slv2
Definition: sys_w11a_c7.vhd:89
out O_RGBLED0_N slv3
Definition: sys_w11a_c7.vhd:91
out O_TXD slbit
Definition: sys_w11a_c7.vhd:88
in I_RXD slbit
Definition: sys_w11a_c7.vhd:87
out O_MEM_WE_N slbit
Definition: sys_w11a_c7.vhd:93
inout IO_MEM_DATA slv8
Definition: sys_w11a_c7.vhd:97
out O_MEM_CE_N slbit
Definition: sys_w11a_c7.vhd:92
out O_MEM_OE_N slbit
Definition: sys_w11a_c7.vhd:94
out O_MEM_ADDR slv19
Definition: sys_w11a_c7.vhd:95
out O_LED slv2
Definition: sys_w11a_c7.vhd:90
in I_CLK12 slbit
Definition: sys_w11a_c7.vhd:86
CLK_MHZ integer := 250
RB_ADDR slv16 := x"fb00"
in RB_MREQ rb_mreq_type
out RB_SRES rb_sres_type
in RESET slbit := '0'
Definition: xlib.vhd:35