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W11 CPU core and support modules
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sys_w11a_n2.vhd
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1-- $Id: sys_w11a_n2.vhd 1325 2022-12-07 11:52:36Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2010-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_w11a_n2 - syn
7-- Description: w11a test design for nexys2
8--
9-- Dependencies: vlib/xlib/dcm_sfs
10-- vlib/genlib/clkdivce
11-- bplib/bpgen/bp_rs232_2l4l_iob
12-- bplib/fx2rlink/rlink_sp1c_fx2
13-- w11a/pdp11_sys70
14-- ibus/ibdr_maxisys
15-- bplib/nxcramlib/nx_cram_memctl_as
16-- bplib/fx2rlink/ioleds_sp1c_fx2
17-- w11a/pdp11_hio70
18-- bplib/bpgen/sn_humanio_rbus
19-- vlib/rbus/rb_sres_or_2
20--
21-- Test bench: tb/tb_sys_w11a_n2
22--
23-- Target Devices: generic
24-- Tool versions: xst 8.2-14.7; ghdl 0.26-2.0.0
25--
26-- Synthesized (xst):
27-- Date Rev ise Target flop lutl lutm slic t peri
28-- 2022-12-06 1324 14.7 131013 xc3s1200e-4 3225 9040 638 5848 ok: 67%
29-- 2019-05-19 1150 14.7 131013 xc3s1200e-4 3219 8981 638 5796 ok: +dz11 66%
30-- 2019-04-27 1140 14.7 131013 xc3s1200e-4 3087 ???? 588 5515 ok: +*buf 63%
31-- 2019-03-02 1116 14.7 131013 xc3s1200e-4 3024 8246 526 5322 ok: +ibtst 61%
32-- 2019-01-27 1108 14.7 131013 xc3s1200e-4 2976 8101 510 5201 ok: -iist
33-- 2018-10-13 1055 14.7 131013 xc3s1200e-4 3097 8484 510 5471 ok: +dmpcnt
34-- 2018-09-15 1045 14.7 131013 xc3s1200e-4 2860 7983 446 5098 ok: +KW11P
35-- 2017-04-30 888 14.7 131013 xc3s1200e-4 2806 7865 446 5043 ok: +fx2dbg
36-- 2017-03-04 858 14.7 131013 xc3s1200e-4 2740 7713 446 4912 ok: +DEUNA
37-- 2017-01-29 846 14.7 131013 xc3s1200e-4 2696 7620 446 4857 ok: +int24
38-- 2015-06-21 692 14.7 131013 xc3s1200e-4 2312 6716 414 4192 ok: rhrp fixes
39-- 2015-06-04 686 14.7 131013 xc3s1200e-4 2311 6725 414 4198 ok: +TM11
40-- 2015-05-14 680 14.7 131013 xc3s1200e-4 2232 6547 414 4083 ok: +RHRP
41-- 2015-02-21 649 14.7 131013 xc3s1200e-4 1903 5512 382 3483 ok: +RL11
42-- 2014-12-22 619 14.7 131013 xc3s1200e-4 1828 5131 366 3263 ok: +rbmon
43-- 2014-12-20 614 14.7 131013 xc3s1200e-4 1714 4896 366 3125 ok: -RL11,rlv4
44-- 2014-06-08 561 14.7 131013 xc3s1200e-4 1626 4821 360 3052 ok: +RL11
45-- 2014-06-01 558 14.7 131013 xc3s1200e-4 1561 4597 334 2901 ok:
46-- 2013-04-20 509 13.3 O76d xc3s1200e-4 1541 4598 334 2889 ok: now + FX2 !
47-- 2011-12-18 440 13.1 O40d xc3s1200e-4 1450 4439 270 2740 ok: LP+PC+DL+II
48-- 2011-11-18 427 13.1 O40d xc3s1200e-4 1433 4374 242 2680 ok: LP+PC+DL+II
49-- 2010-12-30 351 12.1 M53d xc3s1200e-4 1389 4368 242 2674 ok: LP+PC+DL+II
50-- 2010-11-06 336 12.1 M53d xc3s1200e-4 1357 4304* 242 2618 ok: LP+PC+DL+II
51-- 2010-10-24 335 12.1 M53d xc3s1200e-4 1357 4546 242 2618 ok: LP+PC+DL+II
52-- 2010-10-17 333 12.1 M53d xc3s1200e-4 1350 4541 242 2617 ok: LP+PC+DL+II
53-- 2010-10-16 332 12.1 M53d xc3s1200e-4 1338 4545 242 2629 ok: LP+PC+DL+II
54-- 2010-06-27 310 12.1 M53d xc3s1200e-4 1337 4307 242 2630 ok: LP+PC+DL+II
55-- 2010-06-26 309 11.4 L68 xc3s1200e-4 1318 4293 242 2612 ok: LP+PC+DL+II
56-- 2010-06-18 306 12.1 M53d xc3s1200e-4 1319 4300 242 2624 ok: LP+PC+DL+II
57-- " 306 11.4 L68 xc3s1200e-4 1319 4286 242 2618 ok: LP+PC+DL+II
58-- " 306 10.1.02 K39 xc3s1200e-4 1309 4311 242 2665 ok: LP+PC+DL+II
59-- " 306 9.2.02 J40 xc3s1200e-4 1316 4259 242 2656 ok: LP+PC+DL+II
60-- " 306 9.1 J30 xc3s1200e-4 1311 4260 242 2643 ok: LP+PC+DL+II
61-- " 306 8.2.03 I34 xc3s1200e-4 1371 4394 242 2765 ok: LP+PC+DL+II
62-- 2010-06-13 305 11.4 L68 xc3s1200e-4 1318 4360 242 2629 ok: LP+PC+DL+II
63-- 2010-06-12 304 11.4 L68 xc3s1200e-4 1323 4201 242 2574 ok: LP+PC+DL+II
64-- 2010-06-03 300 11.4 L68 xc3s1200e-4 1318 4181 242 2572 ok: LP+PC+DL+II
65-- 2010-06-03 299 11.4 L68 xc3s1200e-4 1250 4071 224 2489 ok: LP+PC+DL+II
66-- 2010-05-26 296 11.4 L68 xc3s1200e-4 1284 4079 224 2492 ok: LP+PC+DL+II
67-- Note: till 2010-10-24 lutm included 'route-thru', after only logic
68--
69-- Revision History:
70-- Date Rev Version Comment
71-- 2018-10-13 1055 2.3 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
72-- 2017-04-30 888 2.2 use SWI(7:6) to allow fx2 debug via LEDs
73-- 2016-03-19 748 2.1.1 define rlink SYSID
74-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
75-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70
76-- 2015-04-11 666 1.7.2 rearrange XON handling
77-- 2015-02-21 649 1.7.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux)
78-- 2015-02-15 647 1.7 drop bram and minisys options
79-- 2014-12-24 620 1.6.2 relocate ibus window and hio rbus address
80-- 2014-12-22 619 1.6.1 add rbus monitor rbd_rbmon
81-- 2014-08-28 588 1.6 use new rlink v4 iface generics and 4 bit STAT
82-- 2014-08-15 583 1.5 rb_mreq addr now 16 bit
83-- 2013-04-20 509 1.4 added fx2 (cuff) support; ATOWIDTH=7
84-- 2011-12-23 444 1.3 remove clksys output hack
85-- 2011-12-18 440 1.2.7 use rlink_sp1c
86-- 2011-11-26 433 1.2.6 use nx_cram_(dummy|memctl_as) now
87-- 2011-11-23 432 1.2.5 update O_FLA_CE_N usage
88-- 2011-11-19 427 1.2.4 now numeric_std clean
89-- 2011-11-17 426 1.2.3 use dcm_sfs now
90-- 2011-07-09 391 1.2.2 use now bp_rs232_2l4l_iob
91-- 2011-07-08 390 1.2.1 use now sn_humanio
92-- 2010-12-30 351 1.2 ported to rbv3
93-- 2010-11-27 341 1.1.8 add DCM; new sys_conf consts for mem and clkdiv
94-- 2010-11-13 338 1.1.7 add O_CLKSYS (for DCM derived system clock)
95-- 2010-11-06 336 1.1.6 rename input pin CLK -> I_CLK50
96-- 2010-10-23 335 1.1.5 rename RRI_LAM->RB_LAM;
97-- 2010-06-26 309 1.1.4 use constants for rbus addresses (rbaddr_...)
98-- BUGFIX: resolve rbus address clash hio<->ibr
99-- 2010-06-18 306 1.1.3 change proc_led sensitivity list to avoid xst warn;
100-- rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
101-- remove pdp11_ibdr_rri
102-- 2010-06-13 305 1.1.2 add CP_ADDR, wire up pdp11_core_rri->pdp11_core
103-- 2010-06-12 304 1.1.1 re-do LED driver logic (show cpu modes or cpurust)
104-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
105-- 2010-06-03 300 1.0.2 use default FAWIDTH for rri_core_serport
106-- use s3_humanio_rri
107-- 2010-05-30 297 1.0.1 put MEM_ACT_(R|W) on LED 6,7
108-- 2010-05-28 295 1.0 Initial version (derived from sys_w11a_s3)
109------------------------------------------------------------------------------
110--
111-- w11a test design for nexys2
112-- w11a + rlink + serport + cuff
113--
114-- Usage of Nexys 2 Switches, Buttons, LEDs:
115--
116-- SWI(7:6): select LED display mode
117-- 0x w11 sys70 LED display (further controlled by SWI(3))
118-- 10 FX2 debug: fx2 fifo states
119-- 11 FX2 debug: fx2 fsm states
120-- (5:4): select DSP
121-- 00 abclkdiv & abclkdiv_f
122-- 01 PC
123-- 10 DISPREG
124-- 11 DR emulation
125-- (3): select LED display
126-- 0 overall status
127-- 1 DR emulation
128-- (2) 0 -> int/ext RS242 port for rlink
129-- 1 -> use USB interface for rlink
130-- (1): 1 enable XON
131-- (0): 0 -> main board RS232 port
132-- 1 -> Pmod B/top RS232 port
133--
134-- LEDs if SWI(7) = 0 and SWI(3) = 1
135-- (7:0) DR emulation; shows R0(lower 8 bits) during wait like 11/45+70
136--
137-- LEDs if SWI(7) = 0 and SWI(3) = 0
138-- (7) MEM_ACT_W
139-- (6) MEM_ACT_R
140-- (5) cmdbusy (all rlink access, mostly rdma)
141-- (4:0) if cpugo=1 show cpu mode activity
142-- (4) kernel mode, pri>0
143-- (3) kernel mode, pri=0
144-- (2) kernel mode, wait
145-- (1) supervisor mode
146-- (0) user mode
147-- if cpugo=0 shows cpurust
148-- (4) '1'
149-- (3:0) cpurust code
150--
151-- LEDs if SWI(7) = 1
152-- (7) fifo_ep4
153-- (6) fifo_ep6
154-- (5) fsm_rx
155-- (4) fsm_tx
156-- LEDs if SWI(7) = 1 and SWI(6) = 0
157-- (3) flag_ep4_empty
158-- (2) flag_ep4_almost
159-- (1) flag_ep6_full
160-- (0) flag_ep6_almost
161-- LEDs if SWI(7) = 1 and SWI(6) = 1
162-- (3) fsm_idle
163-- (2) fsm_prep
164-- (1) fsm_disp
165-- (0) fsm_pipe
166--
167-- DP(3:0) shows IO activity
168-- if SWI(2)=0 (serport)
169-- (3): not SER_MONI.txok (shows tx back pressure)
170-- (2): SER_MONI.txact (shows tx activity)
171-- (1): not SER_MONI.rxok (shows rx back pressure)
172-- (0): SER_MONI.rxact (shows rx activity)
173-- if SWI(2)=1 (fx2-usb)
174-- (3): RB_SRES.busy (shows rbus back pressure)
175-- (2): RLB_TXBUSY (shows tx back pressure)
176-- (1): RLB_TXENA (shows tx activity)
177-- (0): RLB_RXVAL (shows rx activity)
178--
179
180library ieee;
181use ieee.std_logic_1164.all;
182use ieee.numeric_std.all;
183
184use work.slvtypes.all;
185use work.xlib.all;
186use work.genlib.all;
187use work.serportlib.all;
188use work.rblib.all;
189use work.rlinklib.all;
190use work.fx2lib.all;
191use work.fx2rlinklib.all;
192use work.bpgenlib.all;
193use work.bpgenrbuslib.all;
194use work.nxcramlib.all;
195use work.iblib.all;
196use work.ibdlib.all;
197use work.pdp11.all;
198use work.sys_conf.all;
199
200-- ----------------------------------------------------------------------------
201
202entity sys_w11a_n2 is -- top level
203 -- implements nexys2_fusp_cuff_aif
204 port (
205 I_CLK50 : in slbit; -- 50 MHz clock
206 I_RXD : in slbit; -- receive data (board view)
207 O_TXD : out slbit; -- transmit data (board view)
208 I_SWI : in slv8; -- n2 switches
209 I_BTN : in slv4; -- n2 buttons
210 O_LED : out slv8; -- n2 leds
211 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
212 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
213 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
214 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
215 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
216 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
217 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
218 O_MEM_CLK : out slbit; -- cram: clock
219 O_MEM_CRE : out slbit; -- cram: command register enable
220 I_MEM_WAIT : in slbit; -- cram: mem wait
221 O_MEM_ADDR : out slv23; -- cram: address lines
222 IO_MEM_DATA : inout slv16; -- cram: data lines
223 O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
224 O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
225 I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
226 I_FUSP_RXD : in slbit; -- fusp: rs232 rx
227 O_FUSP_TXD : out slbit; -- fusp: rs232 tx
228 I_FX2_IFCLK : in slbit; -- fx2: interface clock
229 O_FX2_FIFO : out slv2; -- fx2: fifo address
230 I_FX2_FLAG : in slv4; -- fx2: fifo flags
231 O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
232 O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
233 O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
234 O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
235 IO_FX2_DATA : inout slv8 -- fx2: data lines
236 );
237end sys_w11a_n2;
238
239architecture syn of sys_w11a_n2 is
240
241 signal CLK : slbit := '0';
242
243 signal RESET : slbit := '0';
244 signal CE_USEC : slbit := '0';
245 signal CE_MSEC : slbit := '0';
246
247 signal RXD : slbit := '1';
248 signal TXD : slbit := '0';
249 signal RTS_N : slbit := '0';
250 signal CTS_N : slbit := '0';
251
252 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
253 signal RB_SRES : rb_sres_type := rb_sres_init;
254 signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
255 signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
256
257 signal RB_LAM : slv16 := (others=>'0');
258 signal RB_STAT : slv4 := (others=>'0');
259
260 signal RLB_MONI : rlb_moni_type := rlb_moni_init;
261 signal SER_MONI : serport_moni_type := serport_moni_init;
262 signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
263
264 signal LED70 : slv8 := (others=>'0');
265
266 signal SWI : slv8 := (others=>'0');
267 signal BTN : slv4 := (others=>'0');
268 signal LED : slv8 := (others=>'0');
269 signal DSP_DAT : slv16 := (others=>'0');
270 signal DSP_DP : slv4 := (others=>'0');
271
272 signal GRESET : slbit := '0'; -- general reset (from rbus)
273 signal CRESET : slbit := '0'; -- cpu reset (from cp)
274 signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
275 signal PERFEXT : slv8 := (others=>'0');
276
277 signal EI_PRI : slv3 := (others=>'0');
278 signal EI_VECT : slv9_2 := (others=>'0');
279 signal EI_ACKM : slbit := '0';
280
281 signal CP_STAT : cp_stat_type := cp_stat_init;
282 signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
283
284 signal MEM_REQ : slbit := '0';
285 signal MEM_WE : slbit := '0';
286 signal MEM_BUSY : slbit := '0';
287 signal MEM_ACK_R : slbit := '0';
288 signal MEM_ACT_R : slbit := '0';
289 signal MEM_ACT_W : slbit := '0';
290 signal MEM_ADDR : slv20 := (others=>'0');
291 signal MEM_BE : slv4 := (others=>'0');
292 signal MEM_DI : slv32 := (others=>'0');
293 signal MEM_DO : slv32 := (others=>'0');
294
295 signal MEM_ADDR_EXT : slv22 := (others=>'0');
296
297 signal IB_MREQ : ib_mreq_type := ib_mreq_init;
298 signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
299
300 signal DISPREG : slv16 := (others=>'0');
301 signal ABCLKDIV : slv16 := (others=>'0');
302
303 constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
304 constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
305
306 constant sysid_proj : slv16 := x"0201"; -- w11a
307 constant sysid_board : slv8 := x"02"; -- nexys2
308 constant sysid_vers : slv8 := x"00";
309
310begin
311
312 assert (sys_conf_clksys mod 1000000) = 0
313 report "assert sys_conf_clksys on MHz grid"
314 severity failure;
315
316 DCM : dcm_sfs -- clock generator -------------------
317 generic map (
318 CLKFX_DIVIDE => sys_conf_clkfx_divide,
319 CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
320 CLKIN_PERIOD => 20.0)
321 port map (
322 CLKIN => I_CLK50,
323 CLKFX => CLK,
324 LOCKED => open
325 );
326
327 CLKDIV : clkdivce -- usec/msec clock divider -----------
328 generic map (
329 CDUWIDTH => 6,
330 USECDIV => sys_conf_clksys_mhz,
331 MSECDIV => 1000)
332 port map (
333 CLK => CLK,
334 CE_USEC => CE_USEC,
335 CE_MSEC => CE_MSEC
336 );
337
338 IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ----------------
339 port map (
340 CLK => CLK,
341 RESET => '0',
342 SEL => SWI(0),
343 RXD => RXD,
344 TXD => TXD,
345 CTS_N => CTS_N,
346 RTS_N => RTS_N,
347 I_RXD0 => I_RXD,
348 O_TXD0 => O_TXD,
349 I_RXD1 => I_FUSP_RXD,
350 O_TXD1 => O_FUSP_TXD,
351 I_CTS1_N => I_FUSP_CTS_N,
352 O_RTS1_N => O_FUSP_RTS_N
353 );
354
355 RLINK : rlink_sp1c_fx2 -- rlink for serport + fx2 -----------
356 generic map (
357 BTOWIDTH => 7, -- 128 cycles access timeout
358 RTAWIDTH => 12,
359 SYSID => sysid_proj & sysid_board & sysid_vers ,
360 IFAWIDTH => 5, -- 32 word input fifo
361 OFAWIDTH => 5, -- 32 word output fifo
362 PETOWIDTH => sys_conf_fx2_petowidth,
363 CCWIDTH => sys_conf_fx2_ccwidth,
364 ENAPIN_RLMON => sbcntl_sbf_rlmon,
365 ENAPIN_RBMON => sbcntl_sbf_rbmon,
366 CDWIDTH => 13,
367 CDINIT => sys_conf_ser2rri_cdinit,
368 RBMON_AWIDTH => sys_conf_rbmon_awidth,
369 RBMON_RBADDR => rbaddr_rbmon)
370 port map (
371 CLK => CLK,
372 CE_USEC => CE_USEC,
373 CE_MSEC => CE_MSEC,
374 CE_INT => CE_MSEC,
375 RESET => RESET,
376 ENAXON => SWI(1),
377 ENAFX2 => SWI(2),
378 RXSD => RXD,
379 TXSD => TXD,
380 CTS_N => CTS_N,
381 RTS_N => RTS_N,
382 RB_MREQ => RB_MREQ,
383 RB_SRES => RB_SRES,
384 RB_LAM => RB_LAM,
385 RB_STAT => RB_STAT,
386 RL_MONI => open,
387 RLB_MONI => RLB_MONI,
388 SER_MONI => SER_MONI,
389 FX2_MONI => FX2_MONI,
390 I_FX2_IFCLK => I_FX2_IFCLK,
391 O_FX2_FIFO => O_FX2_FIFO,
392 I_FX2_FLAG => I_FX2_FLAG,
393 O_FX2_SLRD_N => O_FX2_SLRD_N,
394 O_FX2_SLWR_N => O_FX2_SLWR_N,
395 O_FX2_SLOE_N => O_FX2_SLOE_N,
396 O_FX2_PKTEND_N => O_FX2_PKTEND_N,
397 IO_FX2_DATA => IO_FX2_DATA
398 );
399
400 PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
401 PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
402 PERFEXT(2) <= '0'; -- unused (ext_wrflush)
403 PERFEXT(3) <= RLB_MONI.rxval and not RLB_MONI.rxhold; -- ext_rlrxact
404 PERFEXT(4) <= RLB_MONI.rxhold; -- ext_rlrxback
405 PERFEXT(5) <= RLB_MONI.txena and not RLB_MONI.txbusy; -- ext_rltxact
406 PERFEXT(6) <= RLB_MONI.txbusy; -- ext_rltxback
407 PERFEXT(7) <= CE_USEC; -- ext_usec
408
409 SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
410 port map (
411 CLK => CLK,
412 RESET => RESET,
413 RB_MREQ => RB_MREQ,
414 RB_SRES => RB_SRES_CPU,
415 RB_STAT => RB_STAT,
416 RB_LAM_CPU => RB_LAM(0),
417 GRESET => GRESET,
418 CRESET => CRESET,
419 BRESET => BRESET,
420 CP_STAT => CP_STAT,
421 EI_PRI => EI_PRI,
422 EI_VECT => EI_VECT,
423 EI_ACKM => EI_ACKM,
424 PERFEXT => PERFEXT,
425 IB_MREQ => IB_MREQ,
426 IB_SRES => IB_SRES_IBDR,
427 MEM_REQ => MEM_REQ,
428 MEM_WE => MEM_WE,
429 MEM_BUSY => MEM_BUSY,
430 MEM_ACK_R => MEM_ACK_R,
431 MEM_ADDR => MEM_ADDR,
432 MEM_BE => MEM_BE,
433 MEM_DI => MEM_DI,
434 MEM_DO => MEM_DO,
435 DM_STAT_EXP => DM_STAT_EXP
436 );
437
438 IBDR_SYS : ibdr_maxisys -- IO system -------------------------
439 port map (
440 CLK => CLK,
441 CE_USEC => CE_USEC,
442 CE_MSEC => CE_MSEC,
443 RESET => GRESET,
444 BRESET => BRESET,
445 ITIMER => DM_STAT_EXP.se_itimer,
446 IDEC => DM_STAT_EXP.se_idec,
447 CPUSUSP => CP_STAT.cpususp,
448 RB_LAM => RB_LAM(15 downto 1),
449 IB_MREQ => IB_MREQ,
450 IB_SRES => IB_SRES_IBDR,
451 EI_ACKM => EI_ACKM,
452 EI_PRI => EI_PRI,
453 EI_VECT => EI_VECT,
454 DISPREG => DISPREG
455 );
456
457 MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
458
459 CRAMCTL: nx_cram_memctl_as -- memory controller -----------------
460 generic map (
461 READ0DELAY => sys_conf_memctl_read0delay,
462 READ1DELAY => sys_conf_memctl_read1delay,
463 WRITEDELAY => sys_conf_memctl_writedelay)
464 port map (
465 CLK => CLK,
466 RESET => GRESET,
467 REQ => MEM_REQ,
468 WE => MEM_WE,
469 BUSY => MEM_BUSY,
470 ACK_R => MEM_ACK_R,
471 ACK_W => open,
472 ACT_R => MEM_ACT_R,
473 ACT_W => MEM_ACT_W,
474 ADDR => MEM_ADDR_EXT,
475 BE => MEM_BE,
476 DI => MEM_DI,
477 DO => MEM_DO,
478 O_MEM_CE_N => O_MEM_CE_N,
479 O_MEM_BE_N => O_MEM_BE_N,
480 O_MEM_WE_N => O_MEM_WE_N,
481 O_MEM_OE_N => O_MEM_OE_N,
482 O_MEM_ADV_N => O_MEM_ADV_N,
483 O_MEM_CLK => O_MEM_CLK,
484 O_MEM_CRE => O_MEM_CRE,
485 I_MEM_WAIT => I_MEM_WAIT,
486 O_MEM_ADDR => O_MEM_ADDR,
487 IO_MEM_DATA => IO_MEM_DATA
488 );
489
490 O_FLA_CE_N <= '1'; -- keep Flash memory disabled
491
492 LED_IO : ioleds_sp1c_fx2 -- hio leds from serport or fx2 ------
493 port map (
494 CLK => CLK,
495 CE_USEC => CE_USEC,
496 RESET => GRESET,
497 ENAFX2 => SWI(2),
498 RB_SRES => RB_SRES,
499 RLB_MONI => RLB_MONI,
500 SER_MONI => SER_MONI,
501 IOLEDS => DSP_DP
502 );
503
504 ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
505
506 HIO70 : pdp11_hio70 -- hio from sys70 --------------------
507 generic map (
508 LWIDTH => LED'length,
509 DCWIDTH => 2)
510 port map (
511 SEL_LED => SWI(3),
512 SEL_DSP => SWI(5 downto 4),
513 MEM_ACT_R => MEM_ACT_R,
514 MEM_ACT_W => MEM_ACT_W,
515 CP_STAT => CP_STAT,
516 DM_STAT_EXP => DM_STAT_EXP,
517 ABCLKDIV => ABCLKDIV,
518 DISPREG => DISPREG,
519 LED => LED70,
520 DSP_DAT => DSP_DAT
521 );
522
523 proc_fx2leds: process (SWI, LED70, FX2_MONI) -- hio LED handler ------------
524 variable iled : slv8 := (others=>'0');
525 begin
526
527 iled := (others=>'0');
528 if SWI(7) = '0' then
529 iled := LED70;
530 else
531 iled(7) := FX2_MONI.fifo_ep4;
532 iled(6) := FX2_MONI.fifo_ep6;
533 iled(5) := FX2_MONI.fsm_rx;
534 iled(4) := FX2_MONI.fsm_tx;
535 if SWI(6) = '0' then
536 iled(3) := FX2_MONI.flag_ep4_empty;
537 iled(2) := FX2_MONI.flag_ep4_almost;
538 iled(1) := FX2_MONI.flag_ep6_full;
539 iled(0) := FX2_MONI.flag_ep6_almost;
540 else
541 iled(3) := FX2_MONI.fsm_idle;
542 iled(2) := FX2_MONI.fsm_prep;
543 iled(1) := FX2_MONI.fsm_disp;
544 iled(0) := FX2_MONI.fsm_pipe;
545 end if;
546 end if;
547 LED <= iled;
548
549 end process proc_fx2leds;
550
551 HIO : sn_humanio_rbus -- hio manager -----------------------
552 generic map (
553 DEBOUNCE => sys_conf_hio_debounce,
554 RB_ADDR => rbaddr_hio)
555 port map (
556 CLK => CLK,
557 RESET => RESET,
558 CE_MSEC => CE_MSEC,
559 RB_MREQ => RB_MREQ,
560 RB_SRES => RB_SRES_HIO,
561 SWI => SWI,
562 BTN => BTN,
563 LED => LED,
564 DSP_DAT => DSP_DAT,
565 DSP_DP => DSP_DP,
566 I_SWI => I_SWI,
567 I_BTN => I_BTN,
568 O_LED => O_LED,
569 O_ANO_N => O_ANO_N,
570 O_SEG_N => O_SEG_N
571 );
572
573 RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
574 port map (
575 RB_SRES_1 => RB_SRES_CPU,
576 RB_SRES_2 => RB_SRES_HIO,
577 RB_SRES_OR => RB_SRES
578 );
579
580end syn;
Definition: iblib.vhd:33
Definition: pdp11.vhd:123
Definition: rblib.vhd:32
std_logic_vector( 22 downto 0) slv23
Definition: slvtypes.vhd:56
std_logic_vector( 19 downto 0) slv20
Definition: slvtypes.vhd:53
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 8 downto 2) slv9_2
Definition: slvtypes.vhd:65
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic_vector( 21 downto 0) slv22
Definition: slvtypes.vhd:55
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
slv8 :=( others => '0') LED70
slv9_2 :=( others => '0') EI_VECT
slv16 :=( others => '0') DSP_DAT
slbit := '0' RESET
slbit := '0' GRESET
slv8 :=( others => '0') PERFEXT
slv8 :=( others => '0') LED
slv16 := x"ffe8" rbaddr_rbmon
slv16 := x"fef0" rbaddr_hio
slbit := '0' EI_ACKM
slv16 :=( others => '0') DISPREG
fx2ctl_moni_type := fx2ctl_moni_init FX2_MONI
ib_mreq_type := ib_mreq_init IB_MREQ
slbit := '0' MEM_WE
sn_humanio_rbus hiohio
slv3 :=( others => '0') EI_PRI
slbit := '0' MEM_ACT_R
slv4 :=( others => '0') RB_STAT
slv8 :=( others => '0') SWI
slv32 :=( others => '0') MEM_DI
slbit := '0' MEM_BUSY
rb_mreq_type := rb_mreq_init RB_MREQ
serport_moni_type := serport_moni_init SER_MONI
slbit := '0' MEM_REQ
slbit := '0' CE_USEC
slbit := '1' RXD
pdp11_sys70 sys70sys70
slbit := '0' CE_MSEC
slbit := '0' MEM_ACT_W
slv16 :=( others => '0') ABCLKDIV
slv32 :=( others => '0') MEM_DO
rlink_sp1c_fx2 rlinkrlink
rb_sres_type := rb_sres_init RB_SRES
slv4 :=( others => '0') DSP_DP
cp_stat_type := cp_stat_init CP_STAT
slv8 := x"00" sysid_vers
slbit := '0' CLK
rb_sres_type := rb_sres_init RB_SRES_CPU
slv16 := x"0201" sysid_proj
slbit := '0' CTS_N
slv4 :=( others => '0') BTN
slv22 :=( others => '0') MEM_ADDR_EXT
slbit := '0' BRESET
ib_sres_type := ib_sres_init IB_SRES_IBDR
slv16 :=( others => '0') RB_LAM
rb_sres_type := rb_sres_init RB_SRES_HIO
slbit := '0' RTS_N
slbit := '0' MEM_ACK_R
slbit := '0' CRESET
slv4 :=( others => '0') MEM_BE
dm_stat_exp_type := dm_stat_exp_init DM_STAT_EXP
slbit := '0' TXD
slv8 := x"02" sysid_board
rlb_moni_type := rlb_moni_init RLB_MONI
slv20 :=( others => '0') MEM_ADDR
inout IO_FX2_DATA slv8
out O_FUSP_TXD slbit
in I_FX2_IFCLK slbit
in I_CLK50 slbit
out O_TXD slbit
out O_FUSP_RTS_N slbit
in I_RXD slbit
out O_FX2_PKTEND_N slbit
out O_MEM_WE_N slbit
out O_LED slv8
in I_FUSP_CTS_N slbit
in I_BTN slv4
out O_FX2_SLWR_N slbit
out O_MEM_CE_N slbit
out O_SEG_N slv8
in I_FUSP_RXD slbit
in I_FX2_FLAG slv4
out O_FX2_FIFO slv2
in I_MEM_WAIT slbit
out O_MEM_OE_N slbit
out O_MEM_CLK slbit
out O_MEM_ADV_N slbit
out O_MEM_ADDR slv23
out O_MEM_BE_N slv2
inout IO_MEM_DATA slv16
out O_FLA_CE_N slbit
out O_FX2_SLRD_N slbit
out O_FX2_SLOE_N slbit
out O_MEM_CRE slbit
in I_SWI slv8
out O_ANO_N slv4
Definition: xlib.vhd:35