93use ieee.std_logic_1164.
all;
94use ieee.numeric_std.
all;
171 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
172 signal RB_SRES : rb_sres_type := rb_sres_init;
180 signal SER_MONI : serport_moni_type := serport_moni_init;
190 signal CP_STAT : cp_stat_type := cp_stat_init;
204 signal MIG_MONI : sramif2migui_moni_type := sramif2migui_moni_init;
208 signal IB_MREQ : ib_mreq_type := ib_mreq_init;
231 assert (sys_conf_clksys mod 1000000) = 0
232 report "assert sys_conf_clksys on MHz grid"
243 CLKIN_PERIOD =>
10.0,
244 CLKIN_JITTER =>
0.01,
245 STARTUP_WAIT => false,
246 CLK0_VCODIV => sys_conf_clksys_vcodivide,
247 CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
248 CLK0_OUTDIV => sys_conf_clksys_outdivide,
249 CLK0_GENTYPE => sys_conf_clksys_gentype,
251 CLK0_USECDIV => sys_conf_clksys_mhz,
252 CLK0_MSECDIV =>
1000,
253 CLK1_VCODIV => sys_conf_clkser_vcodivide,
254 CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
255 CLK1_OUTDIV => sys_conf_clkser_outdivide,
256 CLK1_GENTYPE => sys_conf_clkser_gentype,
258 CLK1_USECDIV => sys_conf_clkser_mhz,
259 CLK1_MSECDIV =>
1000,
264 CLK23_GENTYPE =>
"PLL")
300 SYSID => sysid_proj & sysid_board & sysid_vers ,
303 ENAPIN_RLMON => sbcntl_sbf_rlmon,
304 ENAPIN_RBMON => sbcntl_sbf_rbmon,
306 CDINIT => sys_conf_ser2rri_cdinit,
307 RBMON_AWIDTH => sys_conf_rbmon_awidth,
340 SYS70 :
pdp11_sys70 --
1 cpu system ----------------------
369 IBDR_SYS :
ibdr_maxisys -- IO system -------------------------
376 ITIMER => DM_STAT_EXP.se_itimer,
377 IDEC => DM_STAT_EXP.se_idec,
378 CPUSUSP => CP_STAT.cpususp,
379 RB_LAM =>
RB_LAM(15 downto 1),
483 CLK_MHZ => sys_conf_clksys_mhz,
504 RB_SRES_OR :
rb_sres_or_3 -- rbus
or ---------------------------
out O_LED slv( LWIDTH- 1 downto 0)
out SWI slv( SWIDTH- 1 downto 0)
in I_BTN slv( BWIDTH- 1 downto 0)
in I_SWI slv( SWIDTH- 1 downto 0)
out BTN slv( BWIDTH- 1 downto 0)
in LED slv( LWIDTH- 1 downto 0)
in DM_STAT_EXP dm_stat_exp_type
std_logic_vector( 13 downto 0) slv14
std_logic_vector( 19 downto 0) slv20
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 11 downto 0) slv12
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 8 downto 2) slv9_2
std_logic_vector( 0 downto 0) slv1
std_logic_vector( 31 downto 0) slv32
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2
slv9_2 :=( others => '0') EI_VECT
slv8 :=( others => '0') PERFEXT
slv16 := x"ffe8" rbaddr_rbmon
slv12 :=( others => '0') XADC_TEMP
slv16 :=( others => '0') DISPREG
slv8 := x"07" sysid_board
ib_mreq_type := ib_mreq_init IB_MREQ
slv3 :=( others => '0') EI_PRI
slv4 :=( others => '0') RGB_R
slv4 :=( others => '0') RB_STAT
sramif2migui_moni_type := sramif2migui_moni_init MIG_MONI
slv32 :=( others => '0') MEM_DI
rb_sres_type := rb_sres_init RB_SRES_SYSMON
rb_mreq_type := rb_mreq_init RB_MREQ
serport_moni_type := serport_moni_init SER_MONI
slv16 :=( others => '0') ABCLKDIV
slv32 :=( others => '0') MEM_DO
rb_sres_type := rb_sres_init RB_SRES
slv4 :=( others => '0') SWI
slv4 :=( others => '0') RGB_G
cp_stat_type := cp_stat_init CP_STAT
slv4 :=( others => '0') RGB_B
rb_sres_type := rb_sres_init RB_SRES_CPU
slv16 := x"0201" sysid_proj
slv4 :=( others => '0') BTN
slv16 := x"fb00" rbaddr_sysmon
ib_sres_type := ib_sres_init IB_SRES_IBDR
rb_sres_type := rb_sres_init RB_SRES_USRACC
slv16 :=( others => '0') RB_LAM
slv4 :=( others => '0') MEM_BE
dm_stat_exp_type := dm_stat_exp_init DM_STAT_EXP
slv4 :=( others => '0') IOLEDS
slv4 :=( others => '0') LED
slv20 :=( others => '0') MEM_ADDR