w11 - vhd 0.794
W11 CPU core and support modules
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sys_w11a_arty.vhd
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1-- $Id: sys_w11a_arty.vhd 1325 2022-12-07 11:52:36Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2018-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_w11a_arty - syn
7-- Description: w11a design for arty (with dram via mig)
8--
9-- Dependencies: vlib/xlib/bufg_unisim
10-- bplib/bpgen/s7_cmt_1ce1ce2c
11-- cdclib/cdc_signal_s1_as
12-- bplib/bpgen/bp_rs232_2line_iob
13-- vlib/rlink/rlink_sp2c
14-- w11a/pdp11_sys70
15-- ibus/ibdr_maxisys
16-- bplib/arty/sramif_mig_arty
17-- vlib/rlink/ioleds_sp1c
18-- pdp11_hio70_arty
19-- bplib/bpgen/bp_swibtnled
20-- bplib/bpgen/rgbdrv_3x4mux
21-- bplib/sysmon/sysmonx_rbus_arty
22-- vlib/rbus/rbd_usracc
23-- vlib/rbus/rb_sres_or_3
24--
25-- Test bench: tb/tb_sys_w11a_arty
26--
27-- Target Devices: generic
28-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0
29--
30-- Synthesized:
31-- Date Rev viv Target flop lutl lutm bram slic
32-- 2022-12-06 1324 2022.1 xc7a35t-1l 6851 8991 872 17.5 3133
33-- 2022-07-05 1247 2022.1 xc7a35t-1l 6842 9218 872 17.5 3210
34-- 2019-05-19 1150 2017.2 xc7a35t-1l 6838 10574 923 17.5 3392 +dz11
35-- 2019-04-27 1140 2017.2 xc7a35t-1l 6706 10249 898 17.0 3380 +*buf
36-- 2019-03-02 1116 2017.2 xc7a35t-1l 6625 10705 836 17.0 3218
37-- 2019-02-02 1108 2018.3 xc7a35t-1l 6579 9839 819 17.0 3225
38-- 2019-02-02 1108 2017.2 xc7a35t-1l 6575 9798 802 17.0 3182
39--
40-- Revision History:
41-- Date Rev Version Comment
42-- 2022-07-05 1247 1.1.2 use bufg_unisim
43-- 2018-12-28 1096 1.1.1 setup reset for sramif_mig_arty
44-- 2018-12-16 1086 1.1 use s7_cmt_1ce1ce2c
45-- 2018-11-18 1072 1.0 Initial version
46-- 2018-11-17 1071 0.1 First draft (derived from sys_w11a_br_arty)
47------------------------------------------------------------------------------
48--
49-- w11a design for arty (using DDR3 memory via MIG)
50-- w11a + rlink + serport
51--
52-- Usage of Arty switches, Buttons, LEDs
53--
54-- SWI(3:0): determine what is displayed in the LEDs and RGBLEDs
55-- 00xy LED shows IO
56-- y=1 enables CPU activities on RGB_G,RGB_R
57-- x=1 enables MEM activities on RGB_B
58-- 0100 LED+RGB give DR emulation 'light show'
59-- 1xyy LED+RGB show low (x=0) or high (x=1) byte of
60-- yy = 00: abclkdiv & abclkdiv_f
61-- 01: PC
62-- 10: DISPREG
63-- 11: DR emulation
64-- LED shows upper, RGB low nibble of the byte selected by x
65--
66-- LED and RGB assignment for SWI=00xy
67-- LED IO activity
68-- (3) not SER_MONI.txok (shows tx back pressure)
69-- (2) SER_MONI.txact (shows tx activity)
70-- (1) not SER_MONI.rxok (shows rx back pressure)
71-- (0) SER_MONI.rxact (shows rx activity)
72-- RGB_G CPU busy (active cpugo=1, enabled with SWI(0))
73-- (3) kernel mode, non-wait, pri>0
74-- (2) kernel mode, non-wait, pri=0
75-- (1) supervisor mode
76-- (0) user mode
77-- RGB_R CPU rust (active cpugo=0, enabled with SWI(0))
78-- (3:0) cpurust code
79-- RGB_B MEM/cmd busy (enabled with SWI(1))
80-- (3) MEM_ACT_W
81-- (2) MEM_ACT_R
82-- (1) cmdbusy (all rlink access, mostly rdma)
83-- (0) not cpugo
84--
85-- LED and RGB assignment for SWI=0100 (DR emulation)
86-- LED DR(15:12)
87-- RGB_B DR(11:08)
88-- RGB_G DR( 7:04)
89-- RGB_R DR( 3:00)
90--
91
92library ieee;
93use ieee.std_logic_1164.all;
94use ieee.numeric_std.all;
95
96use work.slvtypes.all;
97use work.xlib.all;
98use work.cdclib.all;
99use work.serportlib.all;
100use work.rblib.all;
101use work.rbdlib.all;
102use work.rlinklib.all;
103use work.bpgenlib.all;
104use work.sysmonrbuslib.all;
105use work.miglib.all;
106use work.miglib_arty.all;
107use work.iblib.all;
108use work.ibdlib.all;
109use work.pdp11.all;
110use work.sys_conf.all;
111
112-- ----------------------------------------------------------------------------
113
114entity sys_w11a_arty is -- top level
115 -- implements arty_dram_aif
116 port (
117 I_CLK100 : in slbit; -- 100 MHz clock
118 I_RXD : in slbit; -- receive data (board view)
119 O_TXD : out slbit; -- transmit data (board view)
120 I_SWI : in slv4; -- arty switches
121 I_BTN : in slv4; -- arty buttons
122 O_LED : out slv4; -- arty leds
123 O_RGBLED0 : out slv3; -- arty rgb-led 0
124 O_RGBLED1 : out slv3; -- arty rgb-led 1
125 O_RGBLED2 : out slv3; -- arty rgb-led 2
126 O_RGBLED3 : out slv3; -- arty rgb-led 3
127 A_VPWRN : in slv4; -- arty pwrmon (neg)
128 A_VPWRP : in slv4; -- arty pwrmon (pos)
129 DDR3_DQ : inout slv16; -- dram: data in/out
130 DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
131 DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
132 DDR3_ADDR : out slv14; -- dram: address
133 DDR3_BA : out slv3; -- dram: bank address
134 DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
135 DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
136 DDR3_WE_N : out slbit; -- dram: write enable (act.low)
137 DDR3_RESET_N : out slbit; -- dram: reset (act.low)
138 DDR3_CK_P : out slv1; -- dram: clock (diff-p)
139 DDR3_CK_N : out slv1; -- dram: clock (diff-n)
140 DDR3_CKE : out slv1; -- dram: clock enable
141 DDR3_CS_N : out slv1; -- dram: chip select (act.low)
142 DDR3_DM : out slv2; -- dram: data input mask
143 DDR3_ODT : out slv1 -- dram: on-die termination
144 );
145end sys_w11a_arty;
146
147architecture syn of sys_w11a_arty is
148
149 signal CLK100_BUF : slbit := '0';
150
151 signal CLK : slbit := '0';
152
153 signal RESET : slbit := '0';
154 signal CE_USEC : slbit := '0';
155 signal CE_MSEC : slbit := '0';
156
157 signal CLKS : slbit := '0';
158 signal CES_MSEC : slbit := '0';
159
160 signal CLKMIG : slbit := '0';
161 signal CLKREF : slbit := '0';
162
163 signal LOCKED : slbit := '0'; -- raw LOCKED
164 signal LOCKED_CLK : slbit := '0'; -- sync'ed to CLK
165
166 signal GBL_RESET : slbit := '0';
167
168 signal RXD : slbit := '1';
169 signal TXD : slbit := '0';
170
171 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
172 signal RB_SRES : rb_sres_type := rb_sres_init;
173 signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
174 signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
175 signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
176
177 signal RB_LAM : slv16 := (others=>'0');
178 signal RB_STAT : slv4 := (others=>'0');
179
180 signal SER_MONI : serport_moni_type := serport_moni_init;
181
182 signal GRESET : slbit := '0'; -- general reset (from rbus)
183 signal CRESET : slbit := '0'; -- cpu reset (from cp)
184 signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
185 signal PERFEXT : slv8 := (others=>'0');
186
187 signal EI_PRI : slv3 := (others=>'0');
188 signal EI_VECT : slv9_2 := (others=>'0');
189 signal EI_ACKM : slbit := '0';
190 signal CP_STAT : cp_stat_type := cp_stat_init;
191 signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
192
193 signal MEM_REQ : slbit := '0';
194 signal MEM_WE : slbit := '0';
195 signal MEM_BUSY : slbit := '0';
196 signal MEM_ACK_R : slbit := '0';
197 signal MEM_ACT_R : slbit := '0';
198 signal MEM_ACT_W : slbit := '0';
199 signal MEM_ADDR : slv20 := (others=>'0');
200 signal MEM_BE : slv4 := (others=>'0');
201 signal MEM_DI : slv32 := (others=>'0');
202 signal MEM_DO : slv32 := (others=>'0');
203
204 signal MIG_MONI : sramif2migui_moni_type := sramif2migui_moni_init;
205
206 signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
207
208 signal IB_MREQ : ib_mreq_type := ib_mreq_init;
209 signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
210
211 signal DISPREG : slv16 := (others=>'0');
212 signal ABCLKDIV : slv16 := (others=>'0');
213 signal IOLEDS : slv4 := (others=>'0');
214
215 signal SWI : slv4 := (others=>'0');
216 signal BTN : slv4 := (others=>'0');
217 signal LED : slv4 := (others=>'0');
218 signal RGB_R : slv4 := (others=>'0');
219 signal RGB_G : slv4 := (others=>'0');
220 signal RGB_B : slv4 := (others=>'0');
221
222 constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
223 constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
224
225 constant sysid_proj : slv16 := x"0201"; -- w11a
226 constant sysid_board : slv8 := x"07"; -- arty
227 constant sysid_vers : slv8 := x"00";
228
229begin
230
231 assert (sys_conf_clksys mod 1000000) = 0
232 report "assert sys_conf_clksys on MHz grid"
233 severity failure;
234
235 CLK100_BUFG: bufg_unisim
236 port map (
237 I => I_CLK100,
238 O => CLK100_BUF
239 );
240
241 GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
242 generic map (
243 CLKIN_PERIOD => 10.0,
244 CLKIN_JITTER => 0.01,
245 STARTUP_WAIT => false,
246 CLK0_VCODIV => sys_conf_clksys_vcodivide,
247 CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
248 CLK0_OUTDIV => sys_conf_clksys_outdivide,
249 CLK0_GENTYPE => sys_conf_clksys_gentype,
250 CLK0_CDUWIDTH => 7,
251 CLK0_USECDIV => sys_conf_clksys_mhz,
252 CLK0_MSECDIV => 1000,
253 CLK1_VCODIV => sys_conf_clkser_vcodivide,
254 CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
255 CLK1_OUTDIV => sys_conf_clkser_outdivide,
256 CLK1_GENTYPE => sys_conf_clkser_gentype,
257 CLK1_CDUWIDTH => 7,
258 CLK1_USECDIV => sys_conf_clkser_mhz,
259 CLK1_MSECDIV => 1000,
260 CLK23_VCODIV => 1,
261 CLK23_VCOMUL => 10, -- vco 1000 MHz
262 CLK2_OUTDIV => 6, -- mig sys 166.6 MHz
263 CLK3_OUTDIV => 5, -- mig ref 200.0 MHz
264 CLK23_GENTYPE => "PLL")
265 port map (
266 CLKIN => CLK100_BUF,
267 CLK0 => CLK,
268 CE0_USEC => CE_USEC,
269 CE0_MSEC => CE_MSEC,
270 CLK1 => CLKS,
271 CE1_USEC => open,
272 CE1_MSEC => CES_MSEC,
273 CLK2 => CLKMIG,
274 CLK3 => CLKREF,
275 LOCKED => LOCKED
276 );
277
278 CDC_CLK_LOCKED : cdc_signal_s1_as
279 port map (
280 CLKO => CLK,
281 DI => LOCKED,
282 DO => LOCKED_CLK
283 );
284
285 GBL_RESET <= not LOCKED_CLK;
286
287 IOB_RS232 : bp_rs232_2line_iob -- serport iob ----------------------
288 port map (
289 CLK => CLKS,
290 RXD => RXD,
291 TXD => TXD,
292 I_RXD => I_RXD,
293 O_TXD => O_TXD
294 );
295
296 RLINK : rlink_sp2c -- rlink for serport -----------------
297 generic map (
298 BTOWIDTH => 9, -- 512 cycles, for slow mem iface
299 RTAWIDTH => 12,
300 SYSID => sysid_proj & sysid_board & sysid_vers ,
301 IFAWIDTH => 5, -- 32 word input fifo
302 OFAWIDTH => 5, -- 32 word output fifo
303 ENAPIN_RLMON => sbcntl_sbf_rlmon,
304 ENAPIN_RBMON => sbcntl_sbf_rbmon,
305 CDWIDTH => 12,
306 CDINIT => sys_conf_ser2rri_cdinit,
307 RBMON_AWIDTH => sys_conf_rbmon_awidth,
308 RBMON_RBADDR => rbaddr_rbmon)
309 port map (
310 CLK => CLK,
311 CE_USEC => CE_USEC,
312 CE_MSEC => CE_MSEC,
313 CE_INT => CE_MSEC,
314 RESET => RESET,
315 CLKS => CLKS,
316 CES_MSEC => CES_MSEC,
317 ENAXON => '1', -- XON statically enabled !
318 ESCFILL => '0',
319 RXSD => RXD,
320 TXSD => TXD,
321 CTS_N => '0',
322 RTS_N => open,
323 RB_MREQ => RB_MREQ,
324 RB_SRES => RB_SRES,
325 RB_LAM => RB_LAM,
326 RB_STAT => RB_STAT,
327 RL_MONI => open,
328 SER_MONI => SER_MONI
329 );
330
331 PERFEXT(0) <= MIG_MONI.rdrhit; -- ext_rdrhit
332 PERFEXT(1) <= MIG_MONI.wrrhit; -- ext_wrrhit
333 PERFEXT(2) <= MIG_MONI.wrflush; -- ext_wrflush
334 PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
335 PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
336 PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
337 PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
338 PERFEXT(7) <= CE_USEC; -- ext_usec
339
340 SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
341 port map (
342 CLK => CLK,
343 RESET => RESET,
344 RB_MREQ => RB_MREQ,
345 RB_SRES => RB_SRES_CPU,
346 RB_STAT => RB_STAT,
347 RB_LAM_CPU => RB_LAM(0),
348 GRESET => GRESET,
349 CRESET => CRESET,
350 BRESET => BRESET,
351 CP_STAT => CP_STAT,
352 EI_PRI => EI_PRI,
353 EI_VECT => EI_VECT,
354 EI_ACKM => EI_ACKM,
355 PERFEXT => PERFEXT,
356 IB_MREQ => IB_MREQ,
357 IB_SRES => IB_SRES_IBDR,
358 MEM_REQ => MEM_REQ,
359 MEM_WE => MEM_WE,
360 MEM_BUSY => MEM_BUSY,
361 MEM_ACK_R => MEM_ACK_R,
362 MEM_ADDR => MEM_ADDR,
363 MEM_BE => MEM_BE,
364 MEM_DI => MEM_DI,
365 MEM_DO => MEM_DO,
366 DM_STAT_EXP => DM_STAT_EXP
367 );
368
369 IBDR_SYS : ibdr_maxisys -- IO system -------------------------
370 port map (
371 CLK => CLK,
372 CE_USEC => CE_USEC,
373 CE_MSEC => CE_MSEC,
374 RESET => GRESET,
375 BRESET => BRESET,
376 ITIMER => DM_STAT_EXP.se_itimer,
377 IDEC => DM_STAT_EXP.se_idec,
378 CPUSUSP => CP_STAT.cpususp,
379 RB_LAM => RB_LAM(15 downto 1),
380 IB_MREQ => IB_MREQ,
381 IB_SRES => IB_SRES_IBDR,
382 EI_ACKM => EI_ACKM,
383 EI_PRI => EI_PRI,
384 EI_VECT => EI_VECT,
385 DISPREG => DISPREG
386 );
387
388 MEMCTL: sramif_mig_arty -- SRAM to MIG iface -----------------
389 port map (
390 CLK => CLK,
391 RESET => GBL_RESET,
392 REQ => MEM_REQ,
393 WE => MEM_WE,
394 BUSY => MEM_BUSY,
395 ACK_R => MEM_ACK_R,
396 ACK_W => open,
397 ACT_R => MEM_ACT_R,
398 ACT_W => MEM_ACT_W,
399 ADDR => MEM_ADDR,
400 BE => MEM_BE,
401 DI => MEM_DI,
402 DO => MEM_DO,
403 CLKMIG => CLKMIG,
404 CLKREF => CLKREF,
405 TEMP => XADC_TEMP,
406 MONI => MIG_MONI,
407 DDR3_DQ => DDR3_DQ,
408 DDR3_DQS_P => DDR3_DQS_P,
409 DDR3_DQS_N => DDR3_DQS_N,
410 DDR3_ADDR => DDR3_ADDR,
411 DDR3_BA => DDR3_BA,
412 DDR3_RAS_N => DDR3_RAS_N,
413 DDR3_CAS_N => DDR3_CAS_N,
414 DDR3_WE_N => DDR3_WE_N,
415 DDR3_RESET_N => DDR3_RESET_N,
416 DDR3_CK_P => DDR3_CK_P,
417 DDR3_CK_N => DDR3_CK_N,
418 DDR3_CKE => DDR3_CKE,
419 DDR3_CS_N => DDR3_CS_N,
420 DDR3_DM => DDR3_DM,
421 DDR3_ODT => DDR3_ODT
422 );
423
424 LED_IO : ioleds_sp1c -- hio leds from serport -------------
425 port map (
426 SER_MONI => SER_MONI,
427 IOLEDS => IOLEDS
428 );
429
430 ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
431
432 HIO70 : entity work.pdp11_hio70_arty -- hio from sys70 --------------------
433 port map (
434 CLK => CLK,
435 MODE => SWI,
438 CP_STAT => CP_STAT,
440 DISPREG => DISPREG,
441 IOLEDS => IOLEDS,
443 LED => LED,
444 RGB_R => RGB_R,
445 RGB_G => RGB_G,
446 RGB_B => RGB_B
447 );
448
449 HIO : bp_swibtnled
450 generic map (
451 SWIDTH => I_SWI'length,
452 BWIDTH => I_BTN'length,
453 LWIDTH => O_LED'length,
454 DEBOUNCE => sys_conf_hio_debounce)
455 port map (
456 CLK => CLK,
457 RESET => RESET,
458 CE_MSEC => CE_MSEC,
459 SWI => SWI,
460 BTN => BTN,
461 LED => LED,
462 I_SWI => I_SWI,
463 I_BTN => I_BTN,
464 O_LED => O_LED
465 );
466
467 HIORGB : rgbdrv_3x4mux
468 port map (
469 CLK => CLK,
470 RESET => RESET,
471 CE_USEC => CE_USEC,
472 DATR => RGB_R,
473 DATG => RGB_G,
474 DATB => RGB_B,
479 );
480
481 SMRB: sysmonx_rbus_arty -- always instantiated, needed for mig
482 generic map ( -- use default INIT_ (LP: Vccint=0.95)
483 CLK_MHZ => sys_conf_clksys_mhz,
484 RB_ADDR => rbaddr_sysmon)
485 port map (
486 CLK => CLK,
487 RESET => RESET,
488 RB_MREQ => RB_MREQ,
489 RB_SRES => RB_SRES_SYSMON,
490 ALM => open,
491 OT => open,
492 TEMP => XADC_TEMP,
493 VPWRN => A_VPWRN,
494 VPWRP => A_VPWRP
495 );
496
497 UARB : rbd_usracc
498 port map (
499 CLK => CLK,
500 RB_MREQ => RB_MREQ,
502 );
503
504 RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
505 port map (
506 RB_SRES_1 => RB_SRES_CPU,
507 RB_SRES_2 => RB_SRES_SYSMON,
508 RB_SRES_3 => RB_SRES_USRACC,
509 RB_SRES_OR => RB_SRES
510 );
511
512end syn;
DEBOUNCE boolean := true
SWIDTH positive := 4
out O_LED slv( LWIDTH- 1 downto 0)
out SWI slv( SWIDTH- 1 downto 0)
in I_BTN slv( BWIDTH- 1 downto 0)
LWIDTH positive := 4
in I_SWI slv( SWIDTH- 1 downto 0)
out BTN slv( BWIDTH- 1 downto 0)
in CLK slbit
BWIDTH positive := 4
in LED slv( LWIDTH- 1 downto 0)
in RESET slbit := '0'
in CE_MSEC slbit
in I std_ulogic
Definition: bufg_unisim.vhd:29
out O std_ulogic
Definition: bufg_unisim.vhd:27
Definition: iblib.vhd:33
in CP_STAT cp_stat_type
in DM_STAT_EXP dm_stat_exp_type
Definition: pdp11.vhd:123
in CLK slbit
Definition: rbd_usracc.vhd:40
in RB_MREQ rb_mreq_type
Definition: rbd_usracc.vhd:41
out RB_SRES rb_sres_type
Definition: rbd_usracc.vhd:43
Definition: rblib.vhd:32
in CE_USEC slbit
out O_RGBLED3 slv3
in CLK slbit
out O_RGBLED0 slv3
out O_RGBLED2 slv3
in RESET slbit := '0'
out O_RGBLED1 slv3
std_logic_vector( 13 downto 0) slv14
Definition: slvtypes.vhd:46
std_logic_vector( 19 downto 0) slv20
Definition: slvtypes.vhd:53
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 11 downto 0) slv12
Definition: slvtypes.vhd:44
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 8 downto 2) slv9_2
Definition: slvtypes.vhd:65
std_logic_vector( 0 downto 0) slv1
Definition: slvtypes.vhd:33
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
slbit := '0' CLKS
slv9_2 :=( others => '0') EI_VECT
slbit := '0' RESET
slbit := '0' GRESET
slv8 :=( others => '0') PERFEXT
slbit := '0' CLK100_BUF
slv16 := x"ffe8" rbaddr_rbmon
slbit := '0' EI_ACKM
slv12 :=( others => '0') XADC_TEMP
slv16 :=( others => '0') DISPREG
slv8 := x"07" sysid_board
ib_mreq_type := ib_mreq_init IB_MREQ
slbit := '0' MEM_WE
bp_swibtnled hiohio
slv3 :=( others => '0') EI_PRI
slv4 :=( others => '0') RGB_R
slbit := '0' CLKMIG
slbit := '0' MEM_ACT_R
slv4 :=( others => '0') RB_STAT
sramif2migui_moni_type := sramif2migui_moni_init MIG_MONI
slv32 :=( others => '0') MEM_DI
rb_sres_type := rb_sres_init RB_SRES_SYSMON
slbit := '0' MEM_BUSY
rb_mreq_type := rb_mreq_init RB_MREQ
serport_moni_type := serport_moni_init SER_MONI
slbit := '0' MEM_REQ
slbit := '0' CE_USEC
slbit := '1' RXD
slbit := '0' LOCKED_CLK
slbit := '0' CE_MSEC
slbit := '0' MEM_ACT_W
slbit := '0' CES_MSEC
slv16 :=( others => '0') ABCLKDIV
slv32 :=( others => '0') MEM_DO
rlink_sp2c rlinkrlink
rb_sres_type := rb_sres_init RB_SRES
slv4 :=( others => '0') SWI
slv4 :=( others => '0') RGB_G
cp_stat_type := cp_stat_init CP_STAT
slv4 :=( others => '0') RGB_B
slv8 := x"00" sysid_vers
slbit := '0' CLK
rb_sres_type := rb_sres_init RB_SRES_CPU
slv16 := x"0201" sysid_proj
slv4 :=( others => '0') BTN
slbit := '0' BRESET
slv16 := x"fb00" rbaddr_sysmon
ib_sres_type := ib_sres_init IB_SRES_IBDR
slbit := '0' CLKREF
rb_sres_type := rb_sres_init RB_SRES_USRACC
slv16 :=( others => '0') RB_LAM
slbit := '0' GBL_RESET
slbit := '0' MEM_ACK_R
slbit := '0' CRESET
slv4 :=( others => '0') MEM_BE
dm_stat_exp_type := dm_stat_exp_init DM_STAT_EXP
slbit := '0' TXD
slbit := '0' LOCKED
slv4 :=( others => '0') IOLEDS
slv4 :=( others => '0') LED
slv20 :=( others => '0') MEM_ADDR
out DDR3_CK_P slv1
out DDR3_DM slv2
out O_TXD slbit
in I_RXD slbit
in A_VPWRN slv4
in A_VPWRP slv4
out DDR3_RESET_N slbit
out DDR3_BA slv3
inout DDR3_DQ slv16
out O_RGBLED3 slv3
out DDR3_WE_N slbit
out DDR3_CKE slv1
out DDR3_ADDR slv14
out DDR3_ODT slv1
out DDR3_CAS_N slbit
out DDR3_CK_N slv1
inout DDR3_DQS_P slv2
out O_RGBLED0 slv3
in I_CLK100 slbit
out O_RGBLED2 slv3
inout DDR3_DQS_N slv2
out DDR3_RAS_N slbit
out DDR3_CS_N slv1
out O_RGBLED1 slv3
out O_LED slv4
Definition: xlib.vhd:35